Overview

Areas of using

System level
Verilog is not ideally suited for abstract system-level

Simulation and Synthesis with Verilog

Use Verilog for simulation
Describe modular-hierarchical design
Develop a

Verilog provides mechanism for testbench description and description of hardware
Resulting waveform

Top-down Design Methodology

Bottom-up design methodology

Module declaration

Hardware is described in a module
Module description is bracketed by

Module example

module T_FF (q, clock, reset);
.
.

.
.
endmodule

Levels of description using verilog HDL

Behavioral or algorithmic level
Dataflow level
Gate level
Switch

Design has a hierarchy of modules
A module can completely specify hardware

Illegal module nesting

module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q,

Instances

Design has a hierarchy of modules
A module can completely specify hardware

Example of instances

module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;

Example of instances
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q,

Components of simulation

Components of simulation

Summary

Two kinds of design methodologies are used for digital design: top-down

Lexical Conventions

Comments
A one-line comment - //
A multiple-line comment or

OPERATORS
Operators are of three types:
unary
binary
ternary
a = &b;
a

Number Specification
There are two types of number specification in Verilog
sized

Lexical Conventions

Sized numbers
'
only in decimal and specifies

Lexical Conventions

Legal base formats are
decimal ('d or 'D),
hexadecimal ('h

Lexical Conventions

The number is specified
0, 1, 2, 3, 4, 5,

Lexical Conventions

Examples of sized numbers
5'b01010 // This is a 5-bit

Unsized numbers

Examples
431215 // This is a 32-bit decimal number by default

Lexical Conventions

16'hx13x // This is a 16-bit hex number; 4 least

Lexical Conventions

Underscore characters and question marks
12'b1111_0000_1010 // Use of underline characters

Identifiers and Keywords
Keywords are special identifiers reserved to define the language

Keywords

Identifiers
made up of alphanumeric characters, the underscore ( _ ), or

Identifiers and Keywords

examples
wire temp; // wire is a keyword; temp is

Data Types

Nets represent connections between hardware elements.
Nets are declared primarily with the

Nets Examples
wire a; // Declare net a for the above circuit
wire

Registers

Registers represent data storage elements.
Keyword is reg
Default value for a reg

Example of Register
reg reset;
initial
begin
reset = 1'b1;
#100 reset

Vectors

Nets or reg data types can be declared as vectors
vectors

Vectors examples

wire a; // scalar net variable
wire [7:0] bus; // 8-bit

Arrays

Arrays are allowed in Verilog for reg, integer, time, and vector

Arrays examples

integer count[0:7];
reg bool[31:0];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][0:255];

Examples of assignments to elements of arrays

Examples
count[5] = 0;
chk_point[100]

Memories

Memories are modeled in Verilog as array of registers
reg mem1bit[0:1023];
reg

Parameters

Verilog allows constants to be defined in a module by the

Displaying information

$display("Hello Verilog World");
$display($time);
reg [0:40] virtual_addr;
$display("At time %d

Monitoring information

Usage: $monitor(p1,p2,p3,....,pn);
Unlike $display, $monitor needs to be invoked only

Stopping and finishing in a simulation

The task $stop is provided

Stopping and finishing in a simulation

initial
begin clock = 0;
reset

Components of a Verilog Module

Modules, ports, declarations

Scalar and vector ports
All ports are wires
Initially all values

Port Connection Rules

Connecting Ports to External Signals

Connecting by ordered list
Connecting ports

Hierarchical Names

stimulus stimulus.q
stimulus.qbar stimulus.set
stimulus.reset stimulus.m1
stimulus.m1.Q stimulus.m1.Qbar
stimulus.m1.S stimulus.m1.R
stimulus.n1 stimulus.n2

Gate level combinational parts, using primitives, timing

Verilog allows the use of

Gate Instantiation of And/Or Gates

wire OUT, IN1, IN2;
and a1(OUT, IN1,

Gate Delays

Rise, Fall, and Turn-off Delays
There are three types of delays

Rise Delay

The rise delay is associated with a gate output transition

Fall Delay

The fall delay is associated with a gate output transition

Turn-off delay

The turn-off delay is associated with a gate
output

Types of Delay Specification

// Delay of delay_time for all transitions
and #(delay_time)

Examples of delay specification
and #(5) a1(out, i1, i2);
and #(4,6) a2(out,

Example Min, Max, and Typical Delay Values

// One delay
// if +mindelays,

Example Min, Max, and Typical Delay Values

// Two delays
// if +mindelays,

Example Min, Max, and Typical Delay Values

// Three delays
// if +mindelays,

Delay Example

Delay Example

module D (out, a, b, c);
output out;
input a,b,c;
wire e;
and #(5)

Continuous Assignments

The left hand side of an assignment must always be

Continuous Assignments

The operands on the right-hand side can be registers or

Examples of Continuous Assignment

assign c = a & b;
assign data [31:0]

Implicit Continuous Assignment

/Regular continuous assignment
wire out;
assign out = in1 & in2;
//Same

Implicit Net Declaration

Implicit net declaration is NOT allowed in Verilog 1995.
wire

Delays

regular assignment delay
implicit continuous assignment delay
net declaration delay

Regular Assignment Delay

The delay value is specified after the keyword assign
assign

Implicit Continuous Assignment Delay

An equivalent method is to use an implicit

Net Declaration Delay

//Net Delays
wire # 10 out;
assign out = in1 &

Expressions

Expressions are constructs that combine operators and operands to produce a

Operands

Operands can be constants, integers, real numbers, nets, registers, times, bit-select

Operands : examples

real a, b, c;
c = a - b; //a

Operator Types

Operator Types

Operator Types

Operator Types

Arithmetic Operators

There are two types of arithmetic operators:
binary
unary

Binary operators

Binary arithmetic operators are
multiply (*)
divide (/)
add (+)
subtract

Examples

If any operand bit has a value x, then the result

Logical Operators

Logical operators are
logical-and (&&),
logical-or (||)
logical-not (!).

Logical Operators

Logical operators always evaluate to a 1-bit value, 0

Logical Operators Examples

// Logical operations
A = 3; B = 0;
A && B

// Unknowns
A = 2'b0x; B = 2'b10;
A && B // Evaluates

Relational Operators

Relational operators are
greater-than (>)
less-than (<)
greater-than-or-equal-to (>=)
less-than-or-equal-to (<=)

Equality Operators

Equality operators are
logical equality (==)
logical inequality (!=)

Equality Operators

Equality Operators Examples

// A = 4, B = 3
// X = 4'b1010,

Bitwise Operators

Bitwise operators are
negation (~)
and(&)
or (|)
xor (^)
xnor (^~, ~^)

Bitwise Operators Examples

// X = 4'b1010, Y = 4'b1101
// Z = 4'b10x1
~X

Difference between Logical and Bitwise operators

// X = 4'b1010, Y =

Reduction Operators

Reduction operators are
and (&)
nand (~&)
or (|)

Reduction Operators Examples

// X = 4'b1010
&X //Equivalent to 1 & 0 &

Shift Operators

Shift operators are
right shift ( >>)
left shift (<<)

Shift Operators

// X = 4'b1100
Y = X >> 1; //Y

Concatenation Operator

The concatenation operator is
{, }
// A =

Replication Operator

A replication constant specifies how many times to replicate

Conditional Operator

The conditional operator is
(?:)
and takes three operands.
Usage:
condition_expr

Conditional Operator Examples

//model functionality of a tristate buffer
assign addr_bus = drive_enable ?

Behavioral Modeling

Levels of description using verilog HDL

Behavioral or algorithmic level
Dataflow level
Gate level
Switch

Structured Procedures

There are two structured procedure
statements in Verilog:
always

initial Statement

An initial block starts at time 0, executes exactly

Examples of initial statement

module stimulus;
reg x,y, a,b, m;
initial
m = 1'b0;

always Statement

The always statement starts at time 0 and executes

Example of always statement

module clock_gen (
clock);
output clock;
reg clock;
initial
clock

Procedural Assignments

Procedural assignments update values of reg, integer, real, or

Procedural Assignments

The left-hand side of a procedural assignment can

Procedural Assignments

There are two types of procedural assignment statements:
blocking
nonblocking

Blocking Assignments

Blocking assignment statements are executed in the order they

Example of blocking statement

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
begin

Nonblocking Assignments
A <= operator is used to specify nonblocking assignments.

Nonblocking Assignments Example

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x =

Recomendation

Do not mix blocking and nonblocking
assignments in the same always

Race Conditions

always @(posedge clock)
a = b;
always @(posedge clock)

Eliminate Race Conditions

always @(posedge clock)
a <= b;
always @(posedge clock)

Timing Controls

Delay-based timing control can be specified by a number, identifier,

Regular delay control

x = 0;
#10 y = 1;

Intra-assignment delay control

reg x, y, z;
initial
begin
x = 0; z =

Equivalent method with temporary variables and regular delay control

initial
begin
x

Zero delay control

initial
begin
x = 0;
y = 0;
end
initial
begin
#0 x

Event-Based Timing Control

An event is the change in the value on

Regular event control

The @ symbol is used to specify an event

Regular event control

@(negedge clock) q = d; //q = d is

Named event control

event received_data;
always @(posedge clock)
begin
if(last_data_packet)
->received_data;

Event OR Control

always @ ( reset or clock or d)
begin
if

Not Supported In Verilog 1995

always @ ( reset, clock, d)
begin
if

Not Supported In Verilog 1995

always @(posedge clk, negedge reset)
if(!reset)
q

Suppored by Verilog 1995

always @(a or b or c or d

Level-Sensitive Timing Control

The keyword wait is used for level-sensitive constructs.
always
wait

Conditional Statements Example

//Type 1 statements
if(!lock) buffer = data;
if(enable) out = in;
//Type 2

Conditional Statements Example

//Type 3 statements
//Execute statements based on ALU control signal.
if (alu_control

Multiway Branching

The keywords case, endcase, and default are used in the

Multiway Branching example

//Execute statements based on the ALU control signal
reg [1:0] alu_control;
...
...
case

Multiway Branching example

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input

Loops

There are four types of looping statements in Verilog:
while
for

while Loop

The while loop executes until the while-
expression is not

while Loop example

integer count;
initial
begin
count = 0;
while (count < 128)

for Loop

An initial condition
A check to see if the terminating

for Loop Example

integer count;
initial
for ( count=0; count < 128; count

repeat Loop

The keyword repeat is used for this loop.
integer count;
initial
begin

forever loop

The keyword forever is used to express this
Loop. The

forever loop example

reg clock;
initial
begin
clock = 1'b0;
forever #10 clock =

Sequential and Parallel Blocks

The keywords begin and end are used

Sequential Blocks Example

reg x, y;
reg [1:0] z, w;
initial
begin
x =

Parallel Block Example

reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0;

Special Features of Blocks

There are three special features available with

Nested blocks Example

Blocks can be nested
initial
begin
x = 1'b0;
fork

Named blocks

Blocks can be given names.
Local variables can be declared for

Named Blocks Example

module top;
initial
begin: block1
integer i; // can be

Disabling named blocks

The keyword disable provides a way to
terminate the

Timing and Delays

Types of Delay Models

There are three types of delay models
used

Distributed Delay

Example Distributed Delays

//Distributed delays in gate-level modules
module M (out, a, b,

//Distributed delays in data flow definition of a module
module M (out,

Lumped Delay

Example Lumped Delay

//Lumped Delay Model
module M (out, a, b, c, d);
output

Pin-to-Pin Delays

Path a-e-out delay = 9 Path c-f-out delay =

Path Delay Modeling

path delay - a delay between a source
(input

Specify Blocks

Assign pin-to-pin timing delays across module paths
Set up timing

Specify Blocks

//Pin-to-pin delays
module M (out, a, b, c, d);
output out;
input a,

Parallel connection

A parallel connection is specified by the
symbol =>

Parallel connection

Parallel connection

//bit-to-bit connection. both a and out are single-bit
(a => out)

Illegal parallel connection

//illegal connection. a[4:0] is a 5-bit
//vector, out[3:0] is

Full Conection

A full connection is specified by the symbol *>.
Usage:
(

Full connection

Full Connection example

//Full Connection
module M (out, a, b, c, d);
output out;
input a,

Full Connection

//a[31:0] is a 32-bit vector and out[15:0] is a 16-
//

Edge-Sensitive Paths

if ( RSCEN )
( posedge CLK => ( RSCOUT

specparam statements

//Specify parameters using specparam statement
specify
//define parameters inside the specify

Conditional path delays

specify
if (a) (a => out) = 9;
if (~a) (a

Rise, fall, and turn-off delays

One, two, three, six, or twelve

Rise, fall, and turn-off delays Example

//Specify one delay only. Used for all

Rise, fall, and turn-off delays Example

//Specify three delays, rise, fall, and turn-off
//Rise

Rise, fall, and turn-off delays Example

//specify six delays.
//Delays are specified in order
//for

Rise, fall, and turn-off delays Example

//specify twelve delays.
//Delays are specified in order
//for

Min, max, and typical delays

//Specify three delays, rise, fall, and turn-off
//Each

Handling x transitions

Transitions from x to a known state should

Handling x transitions

//Six delays specified .
//for transitions 0->1, 1->0, 0->z, z->1,

Handling x transitions

0->x min(t_01, t_0z) = 9
1->x min(t_10, t_1z) = 11
z->x

Timing Checks $setup and $hold checks

the setup time is the

$setup and $hold checks

$setup task

Usage:
$setup(data_event, reference_event, limit);
data_event : Signal that is monitored for

$setup task example

specify
$setup(data, posedge clock, 3);
$setup ( RSCEN, posedge CLK,

$hold task

Usage:
$hold (reference_event, data_event, limit);
reference_event
Signal that establishes a

$hold task example

specify
$hold(posedge clear, data, 5);
$hold ( posedge CLK &&&

$width Check

$width Check

Usage:
$width(reference_event, limit);
reference_event
Edge-triggered event (edge transition of a signal)
limit

$width Check example

//width check is set.
//posedge of clear is the reference_event
//the next

Delay Back-Annotation

The designer writes the RTL description and then performs

Delay Back-Annotation

The gate-level netlist is then converted to layout by a

Delay Back-Annotation

Summary

There are three types of delay models: lumped, distributed, and

Summary

Specify blocks are the basic blocks for expressing path delay information.

Summary

Path delays can be conditional or dependent on the values of

Summary

Setup, hold, and width are timing checks that check timing integrity

Timing and Delays

Learning Objectives

Identify types of delay models, distributed, lumped, and pin-to-pin (path)

Learning Objectives

Describe state-dependent path delays.
Explain rise, fall, and turn-off delays. Understand

Types of Delay Models

There are three types of delay models
used

Distributed Delay

Example Distributed Delays

//Distributed delays in gate-level modules
module M (out, a, b,

//Distributed delays in data flow definition of a module
module M (out,

Lumped Delay

Example Lumped Delay

//Lumped Delay Model
module M (out, a, b, c, d);
output

Pin-to-Pin Delays

Path a-e-out delay = 9 Path c-f-out delay =

Path Delay Modeling

path delay - a delay between a source
(input

Specify Blocks

Assign pin-to-pin timing delays across module paths
Set up timing

Specify Blocks

//Pin-to-pin delays
module M (out, a, b, c, d);
output out;
input a,

Parallel connection

A parallel connection is specified by the
symbol =>

Parallel connection

Parallel connection

//bit-to-bit connection. both a and out are single-bit
(a => out)

Illegal parallel connection

//illegal connection. a[4:0] is a 5-bit
//vector, out[3:0] is

Full Conection

A full connection is specified by the symbol *>.
Usage:
(

Full connection

Full Connection example

//Full Connection
module M (out, a, b, c, d);
output out;
input a,

Full Connection

//a[31:0] is a 32-bit vector and out[15:0] is a 16-
//

Edge-Sensitive Paths

if ( RSCEN )
( posedge CLK => ( RSCOUT

specparam statements

//Specify parameters using specparam statement
specify
//define parameters inside the specify

Conditional path delays

specify
if (a) (a => out) = 9;
if (~a) (a

Rise, fall, and turn-off delays

One, two, three, six, or twelve

Rise, fall, and turn-off delays Example

//Specify one delay only. Used for all

Rise, fall, and turn-off delays Example

//Specify three delays, rise, fall, and turn-off
//Rise

Rise, fall, and turn-off delays Example

//specify six delays.
//Delays are specified in order
//for

Rise, fall, and turn-off delays Example

//specify twelve delays.
//Delays are specified in order
//for

Min, max, and typical delays

//Specify three delays, rise, fall, and turn-off
//Each

Handling x transitions

Transitions from x to a known state should

Handling x transitions

//Six delays specified .
//for transitions 0->1, 1->0, 0->z, z->1,

Handling x transitions

0->x min(t_01, t_0z) = 9
1->x min(t_10, t_1z) = 11
z->x

Timing Checks $setup and $hold checks

the setup time is the

$setup and $hold checks

$setup task

Usage:
$setup(data_event, reference_event, limit);
data_event : Signal that is monitored for

$setup task example

specify
$setup(data, posedge clock, 3);
$setup ( RSCEN, posedge CLK,

$hold task

Usage:
$hold (reference_event, data_event, limit);
reference_event
Signal that establishes a

$hold task example

specify
$hold(posedge clear, data, 5);
$hold ( posedge CLK &&&

$width Check

$width Check

Usage:
$width(reference_event, limit);
reference_event
Edge-triggered event (edge transition of a signal)
limit

$width Check example

//width check is set.
//posedge of clear is the reference_event
//the next

Delay Back-Annotation

The designer writes the RTL description and then performs

Delay Back-Annotation

The gate-level netlist is then converted to layout by a

Delay Back-Annotation

Summary

There are three types of delay models: lumped, distributed, and

Summary

Specify blocks are the basic blocks for expressing path delay information.

Summary

Path delays can be conditional or dependent on the values of