!!ADC_DAC_(SAR)

Август 2, 2022

Содержание

2. Agenda Introduction Verilog-A Objectives Sample and Hold Analysis Jitter Noise Thermal noise Model Simulation results Generic
3. Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR
4. Agenda 1.5 bit MDAC Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator SC integrator analysis Model
5. Introduction Transistor-level modeling and simulation is the most accurate approach for mixed-signal circuits. It becomes impractical
6. Introduction This situation has led circuit designers to consider alternate modeling techniques: In addition, behavioral modeling
7. Introduction System Level (Matlab, C++, SystemC, AHDLs, etc…) Functional Level (SPICE, AHDLs) Transistor Level (SPICE) Layout
8. Verilog-A The Verilog-A is a high-level language developed to describe the structure and behavior of analog
9. Objectives Build a set of analog and mixed-signal behavioral models using the Verilog-A AHDL, that allows
10. Agenda Introduction Verilog-A Objectives Sample and Hold Analysis Jitter Noise Thermal noise Model Simulation results Generic
11. Sample and Hold Finite DC gain A0 Finite GBW Cp and CL Defective settling Linear Slewing
12. Clock jitter is due to the non-uniform sampling of the input signal. The magnitude of this
13. Jitter Noise It is assumed that is a Gaussian random process with zero mean and standard
14. Thermal Noise Thermal noise in circuits is because of the random fluctuation of carriers due to
15. Sample and Hold model Ideal S&H + Jitter Defective settling Vout Vout Ideal Nonideal Thermal Noise
16. Sample and Hold simulation results PSD for sampled signal of 0 dB, fin = 2.5146MHz N
17. Agenda Introduction Verilog-A Objectives Sample and Hold Analysis Jitter Noise Thermal noise Model Simulation results Generic
18. Generic DAC Mismatch in DAC units. INL Gain error Offset Mismatch in capacitors! (trimming can reduced
19. Generic DAC model
20. Dynamic Element Matching (DEM) techniques are used to minimize the effect of DAC units mismatch. DAC
21. DEM simulation results By randomizing the DAC units (i.e. using a digital circuitry FSM with a
22. Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR
23. Generic ADC model
24. Generic ADC simulation results gain error =0.5LSB, offset error = 0.5LSB and INL = 0.5LSB SNDR
25. Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR
26. Flash ADC Are made by cascading high-speed comparators. Are the fastest way to convert an analog
27. Flash ADC non-idealities OPAMP Finite DC gain Finite GBW Input resistance Output resistance Bias current Offset
28. Flash ADC simulation results Ideal Nonideal PSD plot for 8-bit Flash ADC with 0 dB input
29. Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR
30. SAR ADC Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits) applications with sample rates
31. SAR ADC
32. 8.0 ENOB 67.353 SFDR (dB) -65.263 THD (dB) 49.949 SNR (dB) 49.823 SNDR (dB) Ideal PSD
33. Ideal SNDR 6.02N+1.76=49.92 dB PSD plot for 8-bit SAR ADC with 0 dB input signal Input
34. Ideal SNDR 6.02N+1.76=49.92 dB PSD plot for 8-bit SAR ADC with 0 dB input signal Input
35. Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR
36. Agenda 1.5 bit MDAC Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator SC integrator analysis Model
37. Pipelined ADC Has become the most popular ADC architecture for sampling rates from a few MS/s
38. Pipeline ADC Stage1 Stage2 Stagek-1 Stagek Registers Digital correction N1 bits N2 bits Nk-1 bits Nk
39. Pipeline ADC 8-bit (1.5-bit per stage ) Stage1 Stage2 Stage6 Registers Digital correction 2 bit 2
40. 1.5-bit Pipelined Stage Vin Residue
41. 1.5-bit ADC
42. 1.5-bit MDAC
43. 1.5-bit MDAC nonidealities Finite DC gain A0 Finite GBW, Cp and CL Defective settling Linear Slewing
44. 1.5-bit Stage model Vin
45. Digital Correction Register Register Register Register Register Register Register Register Register Register Register Register Register Register
46. Pipelined 8-bit ADC model (Cadence)
47. Pipelined 8-bit ADC simulation results PSD plot for 8-bit Pipelined ADC with 0 dB input signal
48. Agenda 1.5 bit MDAC Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator SC integrator analysis Model
49. ΣΔ ADC Makes use of oversampling and ΣΔ modulation techniques to achieve high resolution. Used for
50. ΣΔM is the major analog component of the ADC. Due to its mixed-signal nature, non-idealities largely
51. SC integrator transient model Single pole OTA model Defective settling due to the OTA finite DC
52. Va Second-Order ΣΔΜ Model ∫ g11 g12 ∫ g21 g22 Decoder DAC 3-bits 4-bits 4-bits +
53. ΣΔΜ Simulation Results GSM mode VHDL-AMS 74.0164 dB Actual data 74.5000 dB *Second order sigma-delta modulator
54. ΣΔΜ Simulation Results WCDMA mode VHDL-AMS 45.21 dB Actual data 49.00 dB Second order sigma-delta modulator
55. Conclusions Behavioral modeling is a viable solution for the complex modeling and simulation of mixed-signal circuits.
56. Future Work Include more ADCs architectures such as integrating, sub-range and inter-leaved. Add specific DAC architectures
57. Acknowledgments Dr. Umesh Patel Dr. Manuel Jimenez at UPR Mayaguez Bob Kasa Wesley Powell Ellen Kozireski
58. References M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA CONVERTERS FOR COMMUNICATIONS”, Kluwer
59. References J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA CONVERTERS” PhD Dissertation, University of
60. printf (“Questions?“); #include int main () { } char str [100]; scanf ("%s",str); return 0;
62. Скачать презентацию

Слайд 2

Agenda
Introduction
Verilog-A
Objectives
Sample and Hold
Analysis
Jitter Noise
Thermal noise
Model
Simulation results
Generic DAC
Analysis and model
Dynamic element

matching
Simulation results

Слайд 3

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

model
Simulation Results
Pipelined ADC
Analysis
1.5 bit Stage
1.5 bit ADC

Слайд 4

Agenda
1.5 bit MDAC
Digital Correction
Simulation results
ΣΔ ADC
ΣΔ Modulator
SC integrator analysis
Model
Simulation results
Conclusions
Future Work
Acknowledgements
References

Слайд 5

Introduction
Transistor-level modeling and simulation is the most accurate approach for mixed-signal

circuits.
It becomes impractical for complex systems due to the long computational time required.

Taken form the article: Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A
Nitin Mohan, Sirific Wireless www.techonline.com

Слайд 6

Introduction
This situation has led circuit designers to consider alternate modeling techniques:
In

addition, behavioral modeling can be effectively used in a top-down design approach.

www.techonline.com Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A, Nitin Mohan, Sirific Wireless

Слайд 7

Introduction
System Level
(Matlab, C++, SystemC, AHDLs, etc…)
Functional Level
(SPICE, AHDLs)
Transistor Level
(SPICE)
Layout
Top-Down Design Approach
Behavioral

models

Слайд 8

Verilog-A
The Verilog-A is a high-level language developed to describe the structure

and behavior of analog systems and their components.
It is an extension to the IEEE 1364 Verilog HDL specification for digital design.
The analog systems are described in Verilog-A in a modular way using hierarchy and different levels of modeling complexity.
The motivation is to invest in a new higher level of abstraction in analog design and its combination with the digital one.

`include "constants.vams"
`include "disciplines.vams"
module COMP (vin, vref, vout);
output vout;
electrical vout;
input vin;
electrical vin;
input vref;
electrical vref;
parameter real slope = 100.0;
parameter real offset = 0.0 ;

Слайд 9

Objectives
Build a set of analog and mixed-signal behavioral models using the

Verilog-A AHDL, that allows a high level simulation of ADCs.
Simulate some popular ADCs architectures such as:
Flash ADC
SAR ADC
Pipelined ADC
Simulate other common used mixed-signal circuits such as:
ΣΔ Modulator
Sample and Hold
Provide a general modeling approach for noise sources and other non-idealities.
Provide performance results for the simulated data converters such as spectrum measures SNR, SNDR, THD etc.

Слайд 10

Agenda
Introduction
Verilog-A
Objectives
Sample and Hold
Analysis
Jitter Noise
Thermal noise
Model
Simulation results
Generic DAC
Analysis and model
Dynamic element

matching
Simulation results

Слайд 11

Sample and Hold
Finite DC gain A0
Finite GBW
Cp

and CL
Defective settling
Linear
Slewing
Partial Slewing

Thermal noise
Vth ≈ kT/Cs
(Opamp noise neglected)

εg= 1 - Cs /[ Cs + (Cs + Cp)/A0]

Слайд 12

Clock jitter is due to the non-uniform sampling of the input

signal.
The magnitude of this error is a function of the statistical properties of the jitter and the input signal to the system.
In sampled data systems, when a sinusoidal input is taken, the error introduced by jitter can be modeled by,

Jitter Noise

x(t+δ) - x(t) ≈ 2πfinδAcos(2πfinnt) ≈ δ x(t)

where δ is the sampling uncertainty, this is taken to be a Gaussian random process with standard deviation Δt.

Слайд 13

Jitter Noise
It is assumed that is a Gaussian random process with

zero mean and standard deviation Δt.

Δt

-Δt

Statistical properties of the jitter

Input signal to the system

Слайд 14

Thermal Noise
Thermal noise in circuits is because of the random fluctuation

of carriers due to thermal energy.
Proportional to the temperature.
It is assumed to be a Gaussian random process with zero mean.

Слайд 15

Sample and Hold model
Ideal S&H
+
Jitter
Defective
settling
Vout
Vout
Ideal Nonideal
Thermal
Noise
Vin
τ = RonCs
Filter

Слайд 16

Sample and Hold simulation results
PSD for sampled signal of 0 dB,

fin = 2.5146MHz N = 8192, BW = 25MHz

Increase in noise floor due nonidealities

Слайд 17

Agenda
Introduction
Verilog-A
Objectives
Sample and Hold
Analysis
Jitter Noise
Thermal noise
Model
Simulation results
Generic DAC
Analysis and model
Dynamic element

matching
Simulation results

Слайд 18

Generic DAC
Mismatch in DAC units.
INL
Gain error
Offset
Mismatch in capacitors!
(trimming can reduced it

to 0.1%
Increase in harmonics content)

Слайд 19

Generic DAC model

Слайд 20

Dynamic Element Matching (DEM) techniques are used to minimize the effect

of DAC units mismatch.
DAC DEM techniques can be divided in deterministic and stochastic.
Due to design complexity and non-scalability for modeling purposes it is easier to implement a general stochastic approach using randomization.

DEM

Слайд 21

DEM simulation results
By randomizing the DAC units (i.e. using a digital

circuitry FSM with a system clock) the effect of the mismatch in the spectrum is reduced by reducing the harmonic distortion.

In Verilog-A its rather simple to randomize uniformly the units. Assuming we have a system clock, for each rising edge of the clock signal we randomize the units.
if(DEM_enable) begin
generate i(1,`DAC_UNITS) begin
temp = $dist_uniform(seed, 1, `DAC_UNITS);
if(temp - floor(temp) >= 0.5)
DEM[i] = ceil(temp);
else
DEM[i] = floor(temp); end
end
// Then select units stored in the array DEM[ ] for conversion

Слайд 22

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

model
Simulation Results
Pipelined ADC
Analysis
1.5 bit Stage
1.5 bit ADC

Слайд 23

Generic ADC model

Слайд 24

Generic ADC simulation results
gain error =0.5LSB, offset error = 0.5LSB and

INL = 0.5LSB

SNDR = 49.82 dB
SNR = 49.90 dB
THD = -64.668 dB
SFDR = 67.461 dB
ENOB = 8 bits

PSD plot for 8-bit generic ADC with 0 dB input signal fin of 500.977KHz, Samples = 8192, BW = 2MHz

SNDR = 47.877 dB
SNR = 49.455 dB
THD = -53.037 dB
SFDR = 53.859 dB
ENOB = 7.7 bits

Слайд 25

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

model
Simulation Results
Pipelined ADC
Analysis
1.5 bit Stage
1.5 bit ADC

Слайд 26

Flash ADC
Are made by cascading high-speed comparators.
Are the fastest way

to convert an analog signal to a digital signal.
Ideal for applications requiring very large bandwidth.
Typically consume more power than other ADC architectures and are generally limited to 8-bits resolution.

Слайд 27

Flash ADC non-idealities
OPAMP
Finite DC gain
Finite GBW
Input resistance
Output resistance
Bias current
Offset voltage
Slew Rate
Bubbles
It

is due the metastability of the comparators. (Future work will try model this effect)

Cadence provides a well accepted behavioral model of an non-ideal OPAMP/OTA for the most used AHDLs (Verilog-A, Verilog-AMS and VHDL-AMS)!

Слайд 28

Flash ADC simulation results
Ideal Nonideal
PSD plot for 8-bit Flash ADC with 0

dB input signal fin of 3.01MHz, Samples = 4096, BW = 5MHz

Слайд 29

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

model
Simulation Results
Pipelined ADC
Analysis
1.5 bit Stage
1.5 bit ADC

Слайд 30

SAR ADC
Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits)

applications with sample rates under 5 Msps.
Used in portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition.
Provide low power consumption.
An N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete.

Слайд 31

SAR ADC

Слайд 32

8.0
ENOB
67.353
SFDR (dB)
-65.263
THD (dB)
49.949
SNR (dB)
49.823
SNDR (dB)
Ideal PSD plot for 8-bit SAR ADC

with 0 dB input signal
Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz

SAR 8-bit ADC simulation results

Слайд 33

Ideal SNDR
6.02N+1.76=49.92 dB
PSD plot for 8-bit SAR ADC

with 0 dB input signal
Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz

Increase in harmonics due
mismatch in DAC units

SAR 8-bit ADC simulation results

Слайд 34

Ideal SNDR
6.02N+1.76=49.92 dB
PSD plot for 8-bit SAR ADC

with 0 dB input signal
Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz

Increase in harmonics due
mismatch in DAC units

SAR 8-bit ADC simulation results

Слайд 35

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

model
Simulation Results
Pipelined ADC
Analysis
1.5 bit Stage
1.5 bit ADC

Слайд 36

Agenda
1.5 bit MDAC
Digital Correction
Simulation results
ΣΔ ADC
ΣΔ Modulator
SC integrator analysis
Model
Simulation results
Conclusions
Future Work
Acknowledgements
References

Слайд 37

Pipelined ADC
Has become the most popular ADC architecture for sampling rates

from a few MS/s up to 100MS/s, with resolutions from 8 bits at the faster sample rates up to 16 bits at the lower rates.
Low-power capability.
Allows the use of "digital error correction" and “digital calibration” to greatly reduce the accuracy requirement of the internal flash ADCs and DACs respectively.
Because each sample has to propagate through the entire pipeline before all its associated bits are available there is some data latency.

Слайд 38

Pipeline ADC
Stage1
Stage2
Stagek-1
Stagek
Registers
Digital correction
N1 bits
N2 bits
Nk-1 bits
Nk bits
N1 bits
N2 bits
Nk-1 bits
Nk bits
M

bits

Sample
& hold

Nk-1bit
DAC

Nk-1bit
ADC

k-1

Residue amplifier

Nk-1 bits

Слайд 39

Pipeline ADC 8-bit (1.5-bit per stage )
Stage1
Stage2
Stage6
Registers
Digital correction
2 bit
2 bit
2 bit
2

bits

2 bit

2 bits

8 bits

Sample
& hold

1.5 bit
ADC

Vin

dout

Φ1

Φ2

Φ1

Φ2

Φ1

Φ2

Anti-aliased
signal

Слайд 40

1.5-bit Pipelined Stage
Vin
Residue

Слайд 41

1.5-bit ADC

Слайд 42

1.5-bit MDAC

Слайд 43

1.5-bit MDAC nonidealities
Finite DC gain A0
Finite GBW, Cp

and CL
Defective settling
Linear
Slewing
Partial Slewing

εg= C1+(C1+ C2+ Cp)/A0

Thermal noise Vth ≈ kT/C1
(Opamp noise neglected)

Capacitors mismatch

Слайд 44

1.5-bit Stage model
Vin

Слайд 45

Digital Correction
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
+
+
+
+
+
+
+
b
a
cin
cout
sum
b
a
cin
cout
b
a
cin
cout
b
a
cin
cout
b
a
cin
cout
b
a
cin
cout
b
a
cin
cout
sum
sum
sum
sum
sum
sum
Overflow
s7[1]
s7[0]
s6[1]
s6[0]
s5[1]
s5[0]
s4[1]
s4[0]
s3[1]
s3[0]
s2[1]
s2[0]
s1[1]
s1[0]
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
sk[1] sk[0] are the bits from stage k

Слайд 46

Pipelined 8-bit ADC model (Cadence)

Слайд 47

Pipelined 8-bit ADC simulation results
PSD plot for 8-bit Pipelined ADC with

0 dB input signal
Input frequency of 1.01MHz, Samples = 8192, Bandwidth = 5MHz

Слайд 48

Agenda
1.5 bit MDAC
Digital Correction
Simulation results
ΣΔ ADC
ΣΔ Modulator
SC integrator analysis
Model
Simulation results
Conclusions
Future Work
Acknowledgements
References

Слайд 49

ΣΔ ADC
Makes use of oversampling and ΣΔ modulation techniques to achieve

high resolution.
Used for low bandwidth and high-resolution applications but recently there is great interest for medium to high bandwidth applications.
Due oversampling the requirements of the anti-aliasing filter are reduced.

Слайд 50

ΣΔM is the major analog component of the ADC.
Due to its

mixed-signal nature, non-idealities largely affect the performance of the ADC, i.e. the integrator, DAC mismatch.
Quatization noise is shaped outside the band of interest.
Several architectures exists depending on the number of integrators and the quantizer levels.

ΣΔ Modulator (ΣΔM)

Слайд 51

SC integrator transient model
Single pole OTA model
Defective settling due to the

OTA finite DC gain, GBW and SR limitations.
Possible settling scenarios:
Linear
|Vai| ≤ Io/gm
Slewing
|Vai| > Io/gm and t < to
Partial Slewing
|Vai| > Io/gm and t ≥ to

Слайд 52

Va
Second-Order ΣΔΜ Model
∫
g11
g12
∫
g21
g22
Decoder
DAC
3-bits
4-bits
4-bits
+
Thermal
Noise
+
Thermal
Noise
Jitter
SC intg
OTA + switches for both phases Φ1 and

Φ2

0.1% mismatch

SC intg

gX1 = Ci/Cint
gX2 = Cr/Cint

OTA

Cint

Cinxt

Φ1

Φ2

Φ1

Φ2

Φ1

Φ2

Φ1

Φ2

Φ1

Φ2

Vin

DAC

ILA

4-bits

Слайд 53

ΣΔΜ Simulation Results GSM mode
VHDL-AMS 74.0164 dB
Actual data 74.5000 dB
*Second order

sigma-delta modulator with -6 dB input signal
Input frequency of 30kHz, OSR = 65, N = 65536, BW = 200kHz (GSM mode)

*This work has been accepted as a lecture presentation at the IEEE MWCAS 2005 conference, August 7-10 Cincinnati, Ohio.

0.65% error

Слайд 54

ΣΔΜ Simulation Results WCDMA mode
VHDL-AMS 45.21 dB
Actual data 49.00 dB
Second order

sigma-delta modulator with -6 dB input signal
Input frequency of 300kHz, OSR = 12, N = 65536, BW = 200kHz (GSM mode)

7.7% error

Слайд 55

Conclusions
Behavioral modeling is a viable solution for the complex modeling and

simulation of mixed-signal circuits.
Verilog-A AHDL is suitable for modeling and simulation of mixed-signal circuits providing modularity and flexibility.
Accurate behavioral models are achieved via validation.
Behavioral modeling can be used as part of a Top-Down design approach but an iterative procedure is needed in order to refine the models.
Effective circuits modeling techniques involves deep analysis including noise sources.

Слайд 56

Future Work
Include more ADCs architectures such as integrating, sub-range and inter-leaved.
Add

specific DAC architectures such as resistor-string, capacitive, ΣΔ, multiplying, algorithmic and current-steering.
Explore current based techniques.
Model some other effects in common blocks such as the comparator metastability.
Validate some of the models with available or future designs.

Слайд 57

Acknowledgments
Dr. Umesh Patel
Dr. Manuel Jimenez at UPR Mayaguez
Bob Kasa
Wesley Powell
Ellen

Kozireski
George Schoppet
Alex Dea
Damon Bradley
Aaron Dixon
George Winkert
Betsy Pugel

Слайд 58

References
M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA

CONVERTERS FOR COMMUNICATIONS”, Kluwer Academic Publishers, 2002.
A. Rodriguez-Vazquez, F. Medeiro and E. Janssens. “CMOS Telecom Data Converters”. Kluwer Academic Publishers, 2003.
F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez. “TOP-DOWN ESIGN OF HIGH-PERFORMANCE SIGMA-DELTA MODULATORS”, Kluwer Academic Publishers, 1999.
D. Fitzpatrick and I. Miller. “ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE”, Kluwer Academic Publishers, 1998.
B. Razavi. “Principles of Data Conversion System Design”. IEEE Press, 1995.
T. M. Hancock. S. M. Pernia and A. C. Zeeb. “A Digitally Corrected 1.5-Bit/Stage Low Power 80Ms/s 10-Bit Pipelined ADC”. University of Michigan EECS 598-02, December 2002.
M. Anderson, K. Norling and J. Yuan. “On the Effects of Static Errors in a Pipelined A/D Converter”. SSoCC 2003.
R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K. Einwich, C. Clauss, P Schwarz and G. Noessing. “From System Specifications To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications. Proc. of the 2002 Design, Automation and Test in Europe, 2002.
N. Mohan. “Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A“, www.techonline.com .

Слайд 59

References
J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA CONVERTERS”

PhD Dissertation, University of Nevada Las Vegas , May 2000.
K. Kundert. “Top-Down Design of Mixed-Signal Circuits”. Cadence Design Systems, San Jose, California, 2000.
K. W. Current, J. F. Parker, and W. J. Hardaker, “On Behavioral Modeling of Analog and Mixed-Signal Circuits”. IEEE Conference Record of the Twenty-Eighth Asilomar on Signals, Systems and Computers, vol. 1, pp264 – 268, 1994
F. O. Fernandez “Behavioral Modeling of ΣΔ Modulators”. Master’s Thesis University of Puerto Rico. Mayaguez, Puerto Rico 2003.
T. Kugelstadt. “The operation of the SAR-ADC based on charge redistribution” TI Analog Applications Journal, Texas Instruments, 2000.
J. Compiet, R de Jong, P, Wambacq, G, Vandersteen, S. Donnay, M. Engels and I. Bolsens. “HIGH-LEVEL MODELING OF A HIGH-SPEED FLASH A/D CONVERTER FOR MIXED-SIGNAL SIMULATIONS OF DIGITAL TELECOMMUNICATION FRONT-ENDS”. IEEE SSMSD, pp. 135 – 140, 2000.
B. Brannon. “Aperture Uncertainty and ADC System Performance”. Analog Devices APPLICATION NOTE AN-501.
“Understanding SAR ADCs”. Maxim-IC Application Note 387: Mar 01, 2001.
“Understanding Pipelined ADCs”. Maxim-IC Application Note 383: Mar 01, 2001.
“Understanding Flash ADCs”. Maxim-IC Application Note 810: Oct 02, 2001

Слайд 60

printf (“Questions?“);
#include
int main ()
{
}
char str [100];
scanf

("%s",str);
return 0;

!!ADC_DAC_(SAR)

Содержание

AgendaIntroductionVerilog-AObjectivesSample and HoldAnalysisJitter NoiseThermal noise ModelSimulation resultsGeneric DACAnalysis and modelDynamic element

AgendaGeneric ADCAnalysis and modelSimulation resultsFlash ADCAnalysis and modelSimulation resultsSAR ADCAnalysis and

Agenda1.5 bit MDACDigital CorrectionSimulation resultsΣΔ ADCΣΔ ModulatorSC integrator analysisModelSimulation resultsConclusionsFuture WorkAcknowledgementsReferences

IntroductionTransistor-level modeling and simulation is the most accurate approach for mixed-signal

IntroductionThis situation has led circuit designers to consider alternate modeling techniques:In

IntroductionSystem Level(Matlab, C++, SystemC, AHDLs, etc…)Functional Level(SPICE, AHDLs)Transistor Level(SPICE)LayoutTop-Down Design ApproachBehavioral

Verilog-AThe Verilog-A is a high-level language developed to describe the structure

ObjectivesBuild a set of analog and mixed-signal behavioral models using the

AgendaIntroductionVerilog-AObjectivesSample and HoldAnalysisJitter NoiseThermal noise ModelSimulation resultsGeneric DACAnalysis and modelDynamic element

Sample and Hold Finite DC gain A0 Finite GBW Cp

Clock jitter is due to the non-uniform sampling of the input

Jitter NoiseIt is assumed that is a Gaussian random process with

Thermal NoiseThermal noise in circuits is because of the random fluctuation

Sample and Hold modelIdeal S&H+JitterDefective settlingVoutVoutIdeal NonidealThermalNoiseVinτ = RonCs Filter

Sample and Hold simulation resultsPSD for sampled signal of 0 dB,

AgendaIntroductionVerilog-AObjectivesSample and HoldAnalysisJitter NoiseThermal noise ModelSimulation resultsGeneric DACAnalysis and modelDynamic element

Generic DACMismatch in DAC units.INLGain errorOffsetMismatch in capacitors!(trimming can reduced it

Generic DAC model

Dynamic Element Matching (DEM) techniques are used to minimize the effect

DEM simulation resultsBy randomizing the DAC units (i.e. using a digital

AgendaGeneric ADCAnalysis and modelSimulation resultsFlash ADCAnalysis and modelSimulation resultsSAR ADCAnalysis and

Generic ADC model

Generic ADC simulation resultsgain error =0.5LSB, offset error = 0.5LSB and

AgendaGeneric ADCAnalysis and modelSimulation resultsFlash ADCAnalysis and modelSimulation resultsSAR ADCAnalysis and

Flash ADCAre made by cascading high-speed comparators. Are the fastest way

Flash ADC non-idealitiesOPAMPFinite DC gainFinite GBWInput resistanceOutput resistanceBias currentOffset voltageSlew RateBubblesIt

Flash ADC simulation resultsIdeal NonidealPSD plot for 8-bit Flash ADC with 0

AgendaGeneric ADCAnalysis and modelSimulation resultsFlash ADCAnalysis and modelSimulation resultsSAR ADCAnalysis and

SAR ADCSuccessive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits)

SAR ADC

8.0ENOB67.353SFDR (dB)-65.263THD (dB)49.949SNR (dB)49.823SNDR (dB)Ideal PSD plot for 8-bit SAR ADC

Ideal SNDR 6.02N+1.76=49.92 dBPSD plot for 8-bit SAR ADC

Ideal SNDR 6.02N+1.76=49.92 dBPSD plot for 8-bit SAR ADC

AgendaGeneric ADCAnalysis and modelSimulation resultsFlash ADCAnalysis and modelSimulation resultsSAR ADCAnalysis and

Agenda1.5 bit MDACDigital CorrectionSimulation resultsΣΔ ADCΣΔ ModulatorSC integrator analysisModelSimulation resultsConclusionsFuture WorkAcknowledgementsReferences

Pipelined ADCHas become the most popular ADC architecture for sampling rates

Pipeline ADCStage1Stage2Stagek-1StagekRegistersDigital correctionN1 bitsN2 bitsNk-1 bitsNk bitsN1 bitsN2 bitsNk-1 bitsNk bitsM

Pipeline ADC 8-bit (1.5-bit per stage )Stage1Stage2Stage6RegistersDigital correction2 bit2 bit2 bit2

1.5-bit Pipelined StageVinResidue

1.5-bit ADC

1.5-bit MDAC

1.5-bit MDAC nonidealities Finite DC gain A0 Finite GBW, Cp

1.5-bit Stage modelVin

Pipelined 8-bit ADC model (Cadence)

Pipelined 8-bit ADC simulation resultsPSD plot for 8-bit Pipelined ADC with

Agenda1.5 bit MDACDigital CorrectionSimulation resultsΣΔ ADCΣΔ ModulatorSC integrator analysisModelSimulation resultsConclusionsFuture WorkAcknowledgementsReferences

ΣΔ ADCMakes use of oversampling and ΣΔ modulation techniques to achieve

ΣΔM is the major analog component of the ADC.Due to its

SC integrator transient modelSingle pole OTA modelDefective settling due to the

VaSecond-Order ΣΔΜ Model∫g11g12∫g21g22DecoderDAC3-bits4-bits4-bits+ThermalNoise+ThermalNoiseJitterSC intgOTA + switches for both phases Φ1 and

ΣΔΜ Simulation Results GSM modeVHDL-AMS 74.0164 dBActual data 74.5000 dB*Second order

ΣΔΜ Simulation Results WCDMA modeVHDL-AMS 45.21 dBActual data 49.00 dBSecond order

ConclusionsBehavioral modeling is a viable solution for the complex modeling and

Future WorkInclude more ADCs architectures such as integrating, sub-range and inter-leaved.Add

AcknowledgmentsDr. Umesh PatelDr. Manuel Jimenez at UPR Mayaguez Bob KasaWesley PowellEllen

ReferencesM. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA

ReferencesJ. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA CONVERTERS”

printf (“Questions?“);#include int main () { } char str [100];scanf

Похожие презентации

Agenda
Introduction
Verilog-A
Objectives
Sample and Hold
Analysis
Jitter Noise
Thermal noise
Model
Simulation results
Generic DAC
Analysis and model
Dynamic element

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

Agenda
1.5 bit MDAC
Digital Correction
Simulation results
ΣΔ ADC
ΣΔ Modulator
SC integrator analysis
Model
Simulation results
Conclusions
Future Work
Acknowledgements
References

Introduction
Transistor-level modeling and simulation is the most accurate approach for mixed-signal

Introduction
This situation has led circuit designers to consider alternate modeling techniques:
In

Introduction
System Level
(Matlab, C++, SystemC, AHDLs, etc…)
Functional Level
(SPICE, AHDLs)
Transistor Level
(SPICE)
Layout
Top-Down Design Approach
Behavioral

Verilog-A
The Verilog-A is a high-level language developed to describe the structure

Objectives
Build a set of analog and mixed-signal behavioral models using the

Agenda
Introduction
Verilog-A
Objectives
Sample and Hold
Analysis
Jitter Noise
Thermal noise
Model
Simulation results
Generic DAC
Analysis and model
Dynamic element

Sample and Hold
Finite DC gain A0
Finite GBW
Cp

Jitter Noise
It is assumed that is a Gaussian random process with

Thermal Noise
Thermal noise in circuits is because of the random fluctuation

Sample and Hold model
Ideal S&H
+
Jitter
Defective
settling
Vout
Vout
Ideal Nonideal
Thermal
Noise
Vin
τ = RonCs
Filter

Sample and Hold simulation results
PSD for sampled signal of 0 dB,

Agenda
Introduction
Verilog-A
Objectives
Sample and Hold
Analysis
Jitter Noise
Thermal noise
Model
Simulation results
Generic DAC
Analysis and model
Dynamic element

Generic DAC
Mismatch in DAC units.
INL
Gain error
Offset
Mismatch in capacitors!
(trimming can reduced it

DEM simulation results
By randomizing the DAC units (i.e. using a digital

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

Generic ADC simulation results
gain error =0.5LSB, offset error = 0.5LSB and

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

Flash ADC
Are made by cascading high-speed comparators.
Are the fastest way

Flash ADC non-idealities
OPAMP
Finite DC gain
Finite GBW
Input resistance
Output resistance
Bias current
Offset voltage
Slew Rate
Bubbles
It

Flash ADC simulation results
Ideal Nonideal
PSD plot for 8-bit Flash ADC with 0

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

SAR ADC
Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits)

8.0
ENOB
67.353
SFDR (dB)
-65.263
THD (dB)
49.949
SNR (dB)
49.823
SNDR (dB)
Ideal PSD plot for 8-bit SAR ADC

Ideal SNDR
6.02N+1.76=49.92 dB
PSD plot for 8-bit SAR ADC

Ideal SNDR
6.02N+1.76=49.92 dB
PSD plot for 8-bit SAR ADC

Agenda
Generic ADC
Analysis and model
Simulation results
Flash ADC
Analysis and model
Simulation results
SAR ADC
Analysis and

Agenda
1.5 bit MDAC
Digital Correction
Simulation results
ΣΔ ADC
ΣΔ Modulator
SC integrator analysis
Model
Simulation results
Conclusions
Future Work
Acknowledgements
References

Pipelined ADC
Has become the most popular ADC architecture for sampling rates

Pipeline ADC
Stage1
Stage2
Stagek-1
Stagek
Registers
Digital correction
N1 bits
N2 bits
Nk-1 bits
Nk bits
N1 bits
N2 bits
Nk-1 bits
Nk bits
M

Pipeline ADC 8-bit (1.5-bit per stage )
Stage1
Stage2
Stage6
Registers
Digital correction
2 bit
2 bit
2 bit
2

1.5-bit Pipelined Stage
Vin
Residue

1.5-bit MDAC nonidealities
Finite DC gain A0
Finite GBW, Cp

1.5-bit Stage model
Vin

Pipelined 8-bit ADC simulation results
PSD plot for 8-bit Pipelined ADC with

Agenda
1.5 bit MDAC
Digital Correction
Simulation results
ΣΔ ADC
ΣΔ Modulator
SC integrator analysis
Model
Simulation results
Conclusions
Future Work
Acknowledgements
References

ΣΔ ADC
Makes use of oversampling and ΣΔ modulation techniques to achieve

ΣΔM is the major analog component of the ADC.
Due to its

SC integrator transient model
Single pole OTA model
Defective settling due to the

Va
Second-Order ΣΔΜ Model
∫
g11
g12
∫
g21
g22
Decoder
DAC
3-bits
4-bits
4-bits
+
Thermal
Noise
+
Thermal
Noise
Jitter
SC intg
OTA + switches for both phases Φ1 and

ΣΔΜ Simulation Results GSM mode
VHDL-AMS 74.0164 dB
Actual data 74.5000 dB
*Second order

ΣΔΜ Simulation Results WCDMA mode
VHDL-AMS 45.21 dB
Actual data 49.00 dB
Second order

Conclusions
Behavioral modeling is a viable solution for the complex modeling and

Future Work
Include more ADCs architectures such as integrating, sub-range and inter-leaved.
Add

Acknowledgments
Dr. Umesh Patel
Dr. Manuel Jimenez at UPR Mayaguez
Bob Kasa
Wesley Powell
Ellen

References
M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA

References
J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA CONVERTERS”

printf (“Questions?“);
#include
int main ()
{
}
char str [100];
scanf