Tensilica Xtensa

Overview

Background
Changes in progress from Xtensa to Xtensa LX
Automated Development Process
ISA
TIE Language
Benchmarks

Tensilica

Founded in 1997 in Santa Clara, California by a group of

Why?

Embedded application problems with high cost custom designs or low performance

The Problem with RTL

Rapidly increasing number of transistors require more RTL

Tensilica’s Solution

Xtensa
Focusing on design through the processor, and not through hardwired

Xtensa

First appearing in 1999
32-bit microprocessor core with a graphical configuration interface

Xtensa – In a Nutshell

Enables embedded system designers to build better,

Xtensa - Deliverables

Provided as synthesizable RTL cores
Gate count range: 25,000 –

Xtensa – Verification Challenges

To extensively verify the configurable processor to ensure

Xtensa – Basic Architecture

78 instructions
five-stage pipeline that supports single-cycle execution
1 -

Xtensa – Basic Architecture

Processor Configuration
Power Usage: 200mW, 0.25 μm, 1.5V
Clock Speed:

Xtensa - ISA

Priorities used in ISA Development
Code Size, Configurability, Processor Cost,

Xtensa III

With Virtual IP Group developed an MP3 audio decoder for

Xtensa IV

Used white box verification methodology for the original development
Includes 0-In

Xtensa V

350MHz (synthesized), as small as 18K gates (0.25mm2)
More flexible

Xtensa V – Performance Cost Timeline

Xtensa 6

Extremely fast customization path
Three major enhancements from Xtensa V
Auto customize

Xtensa LX

“Fastest processor core ever” – Tensilica
I/O bandwidth, compute parallelism, and

Xtensa 6 Vs Xtensa LX

Xtensa LX

Strongest selling point is performance
DSP operations can be encapsulated into

Xtensa LX Vs General Purpose

Xtensa LX – Traditional Limitations

1 Operation / cycle
Load/Store overhead

Xtensa LX

Options:
Extra load/store unit, wide interfaces, compound instructions
Up to 19 GB/sec

Xtensa LX – Highlights

Lower power usage
I/O throughput at RTL speeds
Outstanding computer

Xtensa LX – Lower Power Useage

Automated the insertion of fine-grain clock

Outstanding Computing Performance

Extensible using FLIX
(Flexible Length Instruction Xtensions)
Similar to VLIW

XPRES Compiler

Powerful synthesis tool
Creates tailored processor descriptions
Run on native C/C++ code

Automated Development

Clients log into website
Accessing Process Generator
Builds a model in RTL

Automated Development

Create special instructions described and written in TIE
TIE semantics allow

Xtensa LX – Basic Architecture

Processor Configuration
Power Usage: 76 μW/MHz , 47

Xtensa LX Architecture

32-bit ALU
1 or 2 Load/Store Model
Registers
32-bit general purpose register

Xtensa LX Architecture

General Purpose AR Register File
32 or 64 registers
Instructions have

Xtensa LX Architecture

Xtensa LX Pipelining

5 or 7 Stage Pipeline Design
5 stage pipeline has

Xtensa LX Instruction Set

ISA consists of 80 core instructions including both

Xtensa LX Instruction Set

Processor Control Instructions
RSR, WSR, XSR
Read Special Register, Write

Xtensa LX ISA – Building Blocks

MUL32
MUL32 adds 32 bit multiplier
MUL16 and

Xtensa LX ISA – Building Blocks

Floating Point Unit
32-bit, single precision, floating-point

Vectra LX DSP Engine

FLIX-based (why it is 64 bits)
Vectra LX instructions

Vectra LX DSP Engine

Tensilica Instruction Extension

Method used to extend the processor’s architecture and instruction

Tensilica Instruction Extension

TIE Compiler
Generates file used to configure software development tools

TIE

Resembles Verilog
More concise than RTL (it omits all sequential logic, pipeline

TIE Queues and Ports

New way to communicate with external devices
Queues: data

TIE

TIE Combines multiple operations into one using:
Fusion
SIMD/Vector Transformation
FLIX

Fusion

Allows you to combine dependent operations into a single instruction
Consider: computing

Fusion

Fuse the two operations into a single TIE instruction
operation AVERAGE{out AR

SIMD/Vector Transformation

Single Instruction, Multiple Data
Fusing instructions into a “vector”
Allows replication of

SIMD/Vector Transformation

Computing four 16-bit averages
Each data vector must be 64 bits

FLIX

Flexible length instruction extension
Key in extreme extensibility
Huge performance gains possible
Code size

FLIX

FLIX - Usage

Used selectively when parallelism is needed
Avoids code bloat
Used seemlessly

XPRES Compiler

Powerful synthesis tool
Creates tailored processor descriptions
Run on native C/C++ code
Three

XPRES Compiler

Analyzes C/C++ code
Generates possible configurations
Compares performance criteria to silicon size

XPRES Compiler - Results

Application dependent
Compute intensive programs
Data intensive programs
More is

XPRES – 4 Program Test

“Bit Manipulator” program
Cut cycles to a third

XPRES – 4 Program Test

H.264 Deblocking Filter
6% performance improvement

XPRES – 4 Program Test

MPEG4 decoder
23% performance increase

XPRES – 4 Program Test

SAD – sum of absolute difference
63% performance

Xtensa Hi-Fi 2 Audio Engine

Add-on package for Xtensa LX
Advantages over common

Xtensa Hi-Fi 2 Audio Engine

Audio packages integrated into an SOC design,

Xtensa Hi-Fi 2 Audio Engine

Uses over 300 audio specific DLP instructions.

Speed-up Example

GSM Audio Codec – written in C
Profiling code using unaltered

Speed-up Example

Viterbi butterfly instruction
Acts like compression for the data
Consists of 8

EEMBC Networking Benchmark

Xtensa LX received highest benchmark ever achieved on the

EEMBC Networking Benchmark

Normalized (per MHz) EEMBC TCPmark
Simulates performance in internet

EEMBC Networking Benchmark

Normalized (by MHz) EEMBC IPmark
Simulates performance in network routers,

EEMBC Networking Benchmark

Total Code Size

How Xtensa Compares

How Xtensa Compares

How Xtensa Compares (cont)

Uses of Xtensa Products

NVIDIA – Licensed Xtensa LX
“We were very

Uses of Xtensa Products

LG Cell Phone
Phone is digital broadcast enabled
Xtensa processor

In case you are wondering..

--Tensilica's announced licensees include Agilent, ALPS, AMCC