Using systemvue’s open FPGA design flow, M8190A Sig Gen, M9703A High Speed Digitizer

Август 6, 2022

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Using systemvue’s open FPGA design flow, M8190A Sig Gen, M9703A High Speed Digitizer

Содержание

2. Hardware Design Using SystemVue SystemVue, Open FPGA Design Flow HDL Files IP Graphical Design Entry Textual/Binary
3. SystemVue Hardware Design Kit Model based graphical design tool Predict hardware behaviors, before committing to a
4. PART I: SystemVue Open FPGA Design Flow SystemVue, Open FPGA Design Flow
5. Automatic HDL Code Generation Provides path to rapid prototyping and hardware implementation Generating hierarchical VHDL/Verilog allows
6. SystemVue FPGA Design Flow SYSTEM LEVEL SystemVue, Open FPGA Design Flow
7. Various fixed point blocks for hardware design symbol mapping 1st half band filtering CIC filter CORDIC
8. Design Optimization Fixed Point Analysis Sweep Analysis Recursive Graphical Design Design1 Design1 Design1 Design1 Design1 SystemVue,
9. Demo One SystemVue general FPGA design flow Native simulation HDL co-simulation HIL co-simulation Hardware in loop
10. PART II: Integrated Design Flow for M9703A Digitizer SystemVue, Open FPGA Design Flow
11. Integrated Hardware Design Flow for Digitizer Realization of rapid real-time application development for high performance wideband
12. Key Benefits of the integrated design flow Early development of Firmware/Software APIs before HW arrives Standard
13. Overview of M9703A High Speed Digitizer SystemVue/FPGA Flow 8 phase-coherent channels (4 when interleaving), 12-bit wideband
14. DPU FPGA user core ADC input format 1-Ch mode (3.2GS/s) 2-Ch mode (1.6GS/s)
15. M9703A FPGA Design Flow Design entry and software simulation M9703A FPGA programming file auto generation M9703A
16. M9703A FPGA Design Flow Design entry and software simulation M9703A FPGA programming file auto generation M9703A
17. M9703A FPGA Design Flow C++ simulation or C++/HDL mixed simulation if HDL codes or Xilinx IP
18. M9703A FPGA Design Flow SystemVue/FPGA Flow Design entry and software simulation
19. M9703A FPGA Design Flow SystemVue/FPGA Flow Design entry and software simulation
20. M9703A FPGA Design Flow SystemVue/FPGA Flow Design entry and software simulation
21. M9703A FPGA Design Flow Design entry and software simulation M9703A FPGA programming file auto generation M9703A
22. M9703A FPGA Design Flow Design entry and software simulation M9703A FPGA programming file auto generation M9703A
23. M9703A FPGA Design Flow M9703A FPGA programming file auto generation SystemVue/FPGA Flow Auto HDL generation and
24. M9703A FPGA Design Flow Design entry and software simulation M9703A FPGA programming file auto generation M9703A
25. M9703A FPGA Design Flow Design entry and software simulation M9703A FPGA programming file auto generation M9703A
26. M9703A FPGA Design Flow SystemVue/FPGA Flow M9703A instrument co-simulation with SystemVue M9703 Cosim Model M9703 Cosim
27. M9703A FPGA Design Flow M9703A instrument co-simulation with SystemVue
28. M9703A FPGA Design Flow M9703A instrument co-simulation with SystemVue
29. Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer AD DDC FIR W Φ
30. Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer What is difference between channels?
31. Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer Signal processing Trigger Sequence ……
32. Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer Block diagram Halfband FIR1 1.6GSaPS
33. SystemVue, Open FPGA Design Flow Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
34. SystemVue, Open FPGA Design Flow Required Hardware: M9703 with FDK option to enable its FPGA programming
35. SystemVue, Open FPGA Design Flow Demo II Setup Guide (…What We Did) Live Demo M9703A FDK
36. SystemVue, Open FPGA Design Flow Demo II Setup Guide (…What We Did) Live Demo Step 3.
37. SystemVue, Open FPGA Design Flow Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
38. Demo II Setup Guide SystemVue Design – Signal Imbalance Correction SystemVue, Open FPGA Design Flow
39. SystemVue, Open FPGA Design Flow Demo II Setup Guide SystemVue Design – Top Level Workspace
40. Demo II Setup Guide SystemVue Design – Chassis Configuration (+External Splitter) SystemVue, Open FPGA Design Flow
41. Demo II Setup Guide SystemVue Design – M9703A Configuration SystemVue, Open FPGA Design Flow
42. SystemVue, Open FPGA Design Flow Demo II Setup Guide SystemVue Design – 5 Step Signal Correction
43. SW simulation step only (no HW) Source M8190 configuration M9703 measurement + calculate filter coefficients from
44. Demo II Setup Guide Cosim Step 1 (no HW) – M9703A Target Setup SystemVue, Open FPGA
45. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 1 (no HW) – M9703A
46. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 1 (no HW) – M9703A
47. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 1 (no HW) – M9703A
48. SW simulation step only (no HW) Source M8190 configuration M9703 measurement + calculate filter coefficients from
49. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 2 – M8190 Source Setup
50. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 2 – Download 15 Sinusoid
51. M8190A Secondary Address 60005 (Cleared) SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step
52. SystemVue, Open FPGA Design Flow M8190A Primary Address 127.0.0.1 (Error) M8190A Secondary Address 60005 (Cleared) Demo
53. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 2 – M8190 Signal Downloader
54. SW simulation step only (no HW) Source M8190 configuration M9703 measurement + calculate filter coefficients from
55. M9703 Cosim Parameters M9703 Connection and Options SystemVue, Open FPGA Design Flow Demo II Setup Guide
56. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 3 – Reference Channel (In1)
57. Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) Magnitude SystemVue, Open FPGA Design
58. Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) Phase SystemVue, Open FPGA Design
59. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 3(1) – Configure M9703A and
60. SW simulation step only (no HW) Source M8190 configuration M9703 measurement + calculate filter coefficients for
61. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 4 – M8190 Source Setup
62. SW simulation step only (no HW) Source M8190 configuration M9703 measurement + calculate filter coefficients for
63. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A Cosim Model
64. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A UI Parameters
65. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A FPGA Path
66. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A FPGA Path
67. SystemVue, Open FPGA Design Flow Default Path (Error) User Path (Cleared) Note: Drive letter must be
68. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A FPGA Setup
69. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A FPGA(0) Programming
70. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5 – M9703A FPGA(1) Programming
71. Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) Magnitude SystemVue, Open FPGA Design
72. Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) Phase SystemVue, Open FPGA Design
73. SystemVue, Open FPGA Design Flow Demo II Setup Guide Cosim Step 5(1) – Configure M9703A and
74. Summary Introduction to SystemVue hardware design kit General SystemVue hardware design flow Integrated FPGA design flow
75. Thank you Questions yahia_tachwali@keysight.com SystemVue/FPGA Flow
76. Backup SystemVue/FPGA Flow
77. M9703A DPU FPGA user core interface DPU FPGA User Core Interface: ADC data stream input Parallel
78. Early development of Firmware/Software API’s Before HW arrives ADC ADC Register Block Reg DDR MEM DDR
79. Standard Conforming Baseband Stimulus and response metrology Available with W1461BP core environment SystemVue “Baseband Verification” Libraries
80. Simplify complex post analysis Fixed to floating point data conversion FFT, Filtering, Re-sampling Time / Frequency
81. Overcome function test limitation of a timing based simulator Traditional analog functions are being moved to
82. Real world system level simulation Digital I/Q BB Modulation Demod & BER TCP/IP client and data
84. Скачать презентацию

Слайд 2

Hardware Design Using SystemVue
SystemVue, Open FPGA Design Flow
HDL Files
IP
Graphical Design Entry
Textual/Binary

Entry

Signal Generation

FPGA Platforms

3rd Party
HDL Simulators

Signal
Analysis

FPGA

Instrument FPGA

System Level Modeling

SystemVue

Слайд 3

SystemVue Hardware Design Kit Model based graphical design tool
Predict hardware behaviors, before

committing to a full FPGA implementation
Cycle-accurate, Bit-true model
Examine bit growth and adjust the word length setting
Detect the event of overflow and underflow
Realistic RTL level design and verification tool
IP integration with custom HDL code import and Xilinx IP integrator
Co-simulation with RTL simulators
ModelSim / QuestaSim and RiveraPRo
Automatic HDL code generation
Functional verification revolution
Combined with communication architect platform SystemVue
Provide direct connection with Keysight instrument and measurement software

Fully parameterized higher level fixed point blocks

Graphical hardware design entry using vendor independent
fixed point primitive models

Hierarchical desktop design environment with integrated display, analysis and co-simulation

SystemVue, Open FPGA Design Flow

Слайд 4

PART I: SystemVue Open FPGA Design Flow
SystemVue, Open FPGA Design Flow

Слайд 5

Automatic HDL Code Generation Provides path to rapid prototyping and hardware implementation

Generating hierarchical VHDL/Verilog allows path to rapid validation
Fast realizations from schematic
Generates HDL co-sim Test bench
Easy model-based polymorphism
Hardware target agnostic and support Xilinx/Altera

Test vector generation : ON

Direct to:
- Xilinx ISE
- Altera Quartus

SystemVue, Open FPGA Design Flow

Слайд 6

SystemVue FPGA Design Flow
SYSTEM LEVEL
SystemVue, Open FPGA Design Flow

Слайд 7

Various fixed point blocks for hardware design
symbol mapping
1st half
band filtering
CIC
filter
CORDIC
modulator
phase accumulator
2nd

half
band filtering

raised cosin
filtering

SystemVue, Open FPGA Design Flow

Слайд 8

Design Optimization
Fixed Point Analysis
Sweep Analysis
Recursive Graphical Design
Design1
Design1
Design1
Design1
Design1
SystemVue, Open FPGA Design Flow

Слайд 9

Demo One SystemVue general FPGA design flow
Native simulation
HDL co-simulation
HIL co-simulation
Hardware

in loop using ML605 Xilinx board for WLAN transmitter design

SystemVue, Open FPGA Design Flow

Слайд 10

PART II: Integrated Design Flow for M9703A Digitizer
SystemVue, Open FPGA Design

Flow

Слайд 11

Integrated Hardware Design Flow for Digitizer
Realization of rapid real-time application development

for high performance wideband digitizer
Integrated flow for algorithm design & simulation, hardware design & implementation
Custom algorithm design and software level simulation
M9703A_Template design
Hardware co-simulation with M9703A_CoSim model
One push button approach for the bit file generation and FPGA programming

SystemVue, Open FPGA Design Flow

Слайд 12

Key Benefits of the integrated design flow
Early development of Firmware/Software APIs

before HW arrives
Standard conforming baseband stimulus and response metrology
Simplify complex post analysis
Overcome function test limitation of a timing based simulator
Real world system level simulation

SystemVue, Open FPGA Design Flow

Слайд 13

Overview of M9703A High Speed Digitizer
SystemVue/FPGA Flow
8 phase-coherent channels (4 when

interleaving), 12-bit wideband digital digitizer/receiver
Up to 1.6 GS/s for 8 channels or up to 3.2 GS/s for 4 channels (interleaving mode)
Input frequency range of DC to 650 MHz (can be extended to DC to 2GHz with –F10 option)
AXIe standard based
Application fields: multi-channel applications in advanced aerospace & defense, RF communications and physics.

Слайд 14

DPU FPGA user core ADC input format

1-Ch mode (3.2GS/s) 2-Ch

mode (1.6GS/s)

Слайд 15

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

auto generation
M9703A instrument co-simulation with SystemVue

SystemVue/FPGA Flow

Overview

Слайд 16

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

auto generation
M9703A instrument co-simulation with SystemVue

SystemVue/FPGA Flow

Overview

Слайд 17

M9703A FPGA Design Flow
C++ simulation or C++/HDL mixed simulation if

HDL codes or Xilinx IP cores are involved in users’ design
Rich resources for testbench creation
Dynamic Data Flow for extracting valid output of users’ design

Top Level Design in SystemVue

Design entry and software simulation

Слайд 18

M9703A FPGA Design Flow
SystemVue/FPGA Flow
Design entry and software simulation

Слайд 19

M9703A FPGA Design Flow
SystemVue/FPGA Flow
Design entry and software simulation

Слайд 20

M9703A FPGA Design Flow
SystemVue/FPGA Flow
Design entry and software simulation

Слайд 21

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

auto generation
M9703A instrument co-simulation with SystemVue

SystemVue/FPGA Flow

Overview

Слайд 22

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

auto generation
M9703A instrument co-simulation with SystemVue

SystemVue/FPGA Flow

Overview

Слайд 23

M9703A FPGA Design Flow
M9703A FPGA programming file auto generation
SystemVue/FPGA Flow
Auto HDL

generation and ports connection

Fully auto scripts to generate bit file

Слайд 24

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

auto generation
M9703A instrument co-simulation with SystemVue

SystemVue/FPGA Flow

Overview

Слайд 25

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

auto generation
M9703A instrument co-simulation with SystemVue

SystemVue/FPGA Flow

Overview

Слайд 26

M9703A FPGA Design Flow
SystemVue/FPGA Flow
M9703A instrument co-simulation with SystemVue
M9703 Cosim Model
M9703

Cosim Model

PCIe

M9703A Co-simulation Model

ADC

M9703A Digitizer

FPGA 0~3

RAM A

RAM B

User Application Design

Control Registers Configuration

FPGA Images

Convert PCIe format data to the native ports format

Place Multiple M9703A Co-simulation models in SystemVue

Link to multiple M9703A digitizers

SystemVue

Слайд 27

M9703A FPGA Design Flow
M9703A instrument co-simulation with SystemVue

Слайд 28

M9703A FPGA Design Flow
M9703A instrument co-simulation with SystemVue

Слайд 29

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
AD
DDC
FIR
W
Φ
∑
AD
DDC
FIR
W
Φ
AD
DDC
FIR
W
Φ
AD
DDC
FIR
W
Φ
Adaptive Algorithm
I
Q
BEAMS
FPGA
RF

Front End

∑

SpectraSys RF Modeling

BB Processor

SystemVue System Level Simulation

Complex Weight Wk update

Hardware implementation for digital down conversion and filtering
Adaptive beam forming algorithm to update weighting vector on the fly

Figure 1. Adaptive Digital Beam Forming Signal Processing

SystemVue, Open FPGA Design Flow

Слайд 30

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
What is

difference between channels?

RF Module

ADC

Wide band digital receiver

DDC

Physical Path Gain

RF Module

ADC

DDC

Multi-channel RF inputs

SystemVue, Open FPGA Design Flow

Слайд 31

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
Signal processing
Trigger

Sequence

……

Trigger Sequence

…

IFFT

Phase & magnitude calculation
FIR filter coefficients update

Single period of reference signal

SystemVue, Open FPGA Design Flow

Слайд 32

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
Block diagram

Halfband

FIR1

1.6GSaPS

800MSaPS

Halfband

FIR2

800MSaPS

00MSaPS

Halfband

FIR3

400MSaPS

00MSaPS

Halfband

FIR1

1.6GSaPS

800MSaPS

Halfband

FIR2

800MSaPS

00MSaPS

Halfband

FIR3

400MSaPS

00MSaPS

FPGA1

sin

NCO

sin

NCO

FPGA0

Complex

FIR Filter

Complex

Reference
Channel

Calibration
Channel

Calculate
FIR
Coefficients

SystemVue, Open FPGA Design Flow

Слайд 33

SystemVue, Open FPGA Design Flow
Realistic Digitizer Application Example Phase & magnitude correction

for multi-channel digitizer

For Simple Video Demo:
YouTube Video : https://www.youtube.com/watch?v=wrQxkgOPQek

Слайд 34

SystemVue, Open FPGA Design Flow
Required Hardware:
M9703 with FDK option to

enable its FPGA programming capability
M9505 AXIe chassis
M9036 AXIe embedded controller or external PC + PCI Express cable
M8190A AWG
1x2 RF Splitter and RF cables
Required Software:
SystemVue 2015.01 or later.
Keysight IO Library
Keysight MD1 High-Speed Digitizer Instrument Drivers and Soft Front Panel
Xilinx ISE: version 14.4 or later (This software required only when you want to re-generate bit file by yourself. Bit file already generated and included in demo example)
89600 VSA software

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer

Слайд 35

SystemVue, Open FPGA Design Flow
Demo II Setup Guide (…What We Did) Live

Demo

M9703A FDK firmware update and License:
Send serial number of your M9703A demo unit to ZARETTI,CHRISTOPHE (K-Switzerland,ex1) christophe_zaretti@keysight.com
Step 1. Ensure that the required software is installed.
Install the common software required below, and then item that applies to your upgrade option
a. Agilent IO Libraries Suite (IOLS)
Version 16.3 update 2 (or higher) is required for this option
b. MD1 software version 1.13.7 (or higher).
1. Available from the Keysight website at : www.keysight.com/find/M9703A
2. After installation you must reboot the controller and allow the instrument drivers to reinstall.
Step 2. Transfer the new license file to EEPROM
a. Copy the M9703A_US00075291_DDC_FDK.epr license file attached to a local folder.
b. Launch the application 'AcqEepromProg.exe', which may be found:
o 32-bit OS: C:\Program Files\Agilent\MD1\bin
o 64-bit OS: C:\Program Files (x86)\Agilent\MD1\bin
c. Select the M9703A_ US00075291_DDC_FDK.epr file copied above.
d. If more than one digitizer is present, be sure to select the correct one from the list
e. The EEPROM upgrade process should only take a few seconds.
f. Close the application.

Слайд 36

SystemVue, Open FPGA Design Flow
Demo II Setup Guide (…What We Did) Live

Demo

Step 3. Verify the operation of the option upgrade
You can try to load the default FDK firmware file with your test application using strInitOptions = "Simulate=false, DriverSetup= CAL=0, UserDpuA=M9703ADPULX2FDK.bit, UserDpuB=M9703ADPULX2FDK.bit, UserDpuC=M9703ADPULX2FDK.bit, UserDpuD=M9703ADPULX2FDK.bit, Trace=false", the custom FDK firmware will be loaded.

Слайд 37

SystemVue, Open FPGA Design Flow
Realistic Digitizer Application Example Phase & magnitude correction

for multi-channel digitizer

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate filter coefficients from reference channel (In1)
Source M8190 signal generation
M9703 compensation applied to target channel (In3)

Слайд 38

Demo II Setup Guide SystemVue Design – Signal Imbalance Correction
SystemVue, Open

FPGA Design Flow

Слайд 39

SystemVue, Open FPGA Design Flow
Demo II Setup Guide SystemVue Design –

Top Level Workspace

Слайд 40

Demo II Setup Guide SystemVue Design – Chassis Configuration (+External Splitter)
SystemVue, Open

FPGA Design Flow

Слайд 41

Demo II Setup Guide SystemVue Design – M9703A Configuration
SystemVue, Open FPGA Design

Flow

Слайд 42

SystemVue, Open FPGA Design Flow
Demo II Setup Guide SystemVue Design – 5

Step Signal Correction

Слайд 43

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

filter coefficients from reference channel (In1)
Source M8190 signal generation
M9703 compensation applied to target channel (In3)

SystemVue, Open FPGA Design Flow

Demo II Setup Guide Cosim Step 1 – SystemVue Design Only

Слайд 44

Demo II Setup Guide Cosim Step 1 (no HW) – M9703A Target

Setup

SystemVue, Open FPGA Design Flow

Cosim Only
(no HW)

M9703A
FPGA

Слайд 45

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 1 (no

HW) – M9703A Template

Слайд 46

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 1 (no

HW) – M9703A User Design

Слайд 47

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 1 (no

HW) – M9703A User Design

Слайд 48

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

filter coefficients from reference channel (In1)
Source M8190 signal generation
M9703 compensation applied to target channel (In3)

SystemVue, Open FPGA Design Flow

Demo II Setup Guide Cosim Step 2 – Source Configuration

Слайд 49

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 2 –

M8190 Source Setup

M8190
Source

15 Sinusoid Sources (Step 2)

Chirped Source (Step 4)

Слайд 50

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 2 –

Download 15 Sinusoid Sources, BW =100 MHz

Слайд 51

M8190A Secondary Address 60005 (Cleared)
SystemVue, Open FPGA Design Flow
Demo II Setup

Guide Cosim Step 2 – M8190 Address Declarations

Слайд 52

SystemVue, Open FPGA Design Flow
M8190A Primary Address
127.0.0.1 (Error)
M8190A Secondary Address

60005 (Cleared)

Demo II Setup Guide Cosim Step 2 – M8190 LAN Connectivity

Слайд 53

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 2 –

M8190 Signal Downloader UI

Слайд 54

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

filter coefficients from reference channel (In1)
Source M8190 signal generation
M9703 compensation applied to target channel (In3)

SystemVue, Open FPGA Design Flow

Demo II Setup Guide Cosim Step 3 – Reference Channel (Uncorrected) Measurement

Слайд 55

M9703 Cosim Parameters
M9703 Connection and Options
SystemVue, Open FPGA Design Flow
Demo II

Setup Guide Cosim Step 3 – M9703A Setup & UI Parameters

Слайд 56

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 3 –

Reference Channel (In1) Measurement Calculation

Слайд 57

Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) Magnitude
SystemVue,

Open FPGA Design Flow

Слайд 58

Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) Phase
SystemVue,

Open FPGA Design Flow

Слайд 59

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 3(1) –

Configure M9703A and Capture Results (VSA)

Note (1): Separate VSA enabled workspace, not req’d.

Слайд 60

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

filter coefficients for reference channel (In1)
Source M8190 signal generation
M9703 compensation applied to target channel (In3)

SystemVue, Open FPGA Design Flow

Demo II Setup Guide Cosim Step 4 – Source Configuration

Слайд 61

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 4 –

M8190 Source Setup

M8190
Source

Sinusoid Sources (Step 2)

Chirped Source (Step 4)

Слайд 62

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

filter coefficients for reference channel (In1)
Source M8190 signal generation
M9703 compensation applied to target channel (In3)

SystemVue, Open FPGA Design Flow

Demo II Setup Guide Cosim Step 5 – Target Channel (Corrected) Measurement

Слайд 63

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A Cosim Model

Слайд 64

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A UI Parameters (Setup Errors)

Слайд 65

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A FPGA Path Correction

Слайд 66

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A FPGA Path Correction Message

Слайд 67

SystemVue, Open FPGA Design Flow
Default Path (Error)
User Path (Cleared)
Note: Drive letter

must
be lowercase.

Demo II Setup Guide Cosim Step 5 – M9703A FPGA Setup Errors

Слайд 68

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A FPGA Setup Errors (Cleared)

Слайд 69

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A FPGA(0) Programming UI

Слайд 70

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

M9703A FPGA(1) Programming UI

Слайд 71

Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) Magnitude
SystemVue,

Open FPGA Design Flow

Слайд 72

Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) Phase
SystemVue,

Open FPGA Design Flow

Слайд 73

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5(1) –

Configure M9703A and Capture Results (VSA)

Note (1): Separate VSA enabled workspace, not req’d.

Слайд 74

Summary
Introduction to SystemVue hardware design kit
General SystemVue hardware design flow
Integrated FPGA

design flow demo for M9703A digitizer

SystemVue, Open FPGA Design Flow

Слайд 75

Thank you Questions yahia_tachwali@keysight.com
SystemVue/FPGA Flow

Слайд 76

Backup
SystemVue/FPGA Flow

Слайд 77

M9703A DPU FPGA user core interface

DPU FPGA User Core Interface:
ADC

data stream input
Parallel input
Two DDR3 memory
WR: AXI4-Stream
RD: AXI4-Full
QDRII memory
WR: AXI4-Stream
RD: AXI4-Full
PCIe connectivity with backplane via PCIe switch
AXI4-Full
AXI4-Lite
Inter FPGAs data stream connectivity
AXI4-Stream

Слайд 78

Early development of Firmware/Software API’s Before HW arrives
ADC
ADC
Register
Block Reg
DDR MEM
DDR MEM
FPGA
M9703_TEMPLATE
SYSTEMVUE
Basic module

configuration and control.
Low-level functions for register-based I/O.
Low-level functions for block-transfers to and from the FPGA and associated memories.
Higher-level APIs for controlling the FPGA

C++ Custom Model Builder

Custom Application and API

SystemVue, Open FPGA Design Flow

Слайд 79

Standard Conforming Baseband Stimulus and response metrology
Available with W1461BP core environment
SystemVue

“Baseband Verification” Libraries

SystemVue Hardware Design

Data type conversion
Floating/Fixed Point

SystemVue, Open FPGA Design Flow

Слайд 80

Simplify complex post analysis
Fixed to floating point data conversion
FFT, Filtering, Re-sampling
Time

/ Frequency domain conversion and plotting
Send out data from SystemVue to user application for further processing and display

SystemVue, Open FPGA Design Flow

Слайд 81

Overcome function test limitation of a timing based simulator
Traditional analog functions

are being moved to DSP - DUC, DDC, DDS, Beam Former, etc…
Need more than timing & logic analysis
How many FPGA designer can see vector analysis results during HDL coding and verification in traditional design flow?

RTL Simulator

Keysight 89600 Vector Analysis Software

SystemVue, Open FPGA Design Flow

Слайд 82

Real world system level simulation
Digital I/Q
BB Modulation
Demod & BER
TCP/IP client

and
data streaming
(control channel from Test Exec)

FPGA Model

Measurement and verification of an FPGA model requiring complex metrics in the presence of real world impairments.

SystemVue, Open FPGA Design Flow

Using systemvue’s open FPGA design flow, M8190A Sig Gen, M9703A High Speed Digitizer

Содержание

Hardware Design Using SystemVueSystemVue, Open FPGA Design FlowHDL FilesIPGraphical Design EntryTextual/Binary

SystemVue Hardware Design Kit Model based graphical design toolPredict hardware behaviors, before

PART I: SystemVue Open FPGA Design FlowSystemVue, Open FPGA Design Flow

Automatic HDL Code Generation Provides path to rapid prototyping and hardware implementation

SystemVue FPGA Design FlowSYSTEM LEVELSystemVue, Open FPGA Design Flow

Various fixed point blocks for hardware designsymbol mapping1st halfband filteringCICfilterCORDICmodulatorphase accumulator2nd

Design OptimizationFixed Point AnalysisSweep AnalysisRecursive Graphical DesignDesign1Design1Design1Design1Design1SystemVue, Open FPGA Design Flow

Demo One SystemVue general FPGA design flowNative simulation HDL co-simulation HIL co-simulationHardware

PART II: Integrated Design Flow for M9703A DigitizerSystemVue, Open FPGA Design

Integrated Hardware Design Flow for Digitizer Realization of rapid real-time application development

Key Benefits of the integrated design flowEarly development of Firmware/Software APIs

Overview of M9703A High Speed DigitizerSystemVue/FPGA Flow8 phase-coherent channels (4 when

DPU FPGA user core ADC input format 1-Ch mode (3.2GS/s) 2-Ch

M9703A FPGA Design FlowDesign entry and software simulation M9703A FPGA programming file

M9703A FPGA Design FlowDesign entry and software simulation M9703A FPGA programming file

M9703A FPGA Design Flow C++ simulation or C++/HDL mixed simulation if

M9703A FPGA Design FlowSystemVue/FPGA FlowDesign entry and software simulation

M9703A FPGA Design FlowSystemVue/FPGA FlowDesign entry and software simulation

M9703A FPGA Design FlowSystemVue/FPGA FlowDesign entry and software simulation

M9703A FPGA Design FlowDesign entry and software simulation M9703A FPGA programming file

M9703A FPGA Design FlowDesign entry and software simulation M9703A FPGA programming file

M9703A FPGA Design FlowM9703A FPGA programming file auto generationSystemVue/FPGA FlowAuto HDL

M9703A FPGA Design FlowDesign entry and software simulation M9703A FPGA programming file

M9703A FPGA Design FlowDesign entry and software simulation M9703A FPGA programming file

M9703A FPGA Design FlowSystemVue/FPGA FlowM9703A instrument co-simulation with SystemVueM9703 Cosim ModelM9703

M9703A FPGA Design FlowM9703A instrument co-simulation with SystemVue

M9703A FPGA Design FlowM9703A instrument co-simulation with SystemVue

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizerADDDCFIRWΦ∑ADDDCFIRWΦADDDCFIRWΦADDDCFIRWΦAdaptive AlgorithmIQBEAMSFPGARF

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizerWhat is

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizerSignal processingTrigger

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizerBlock diagram

SystemVue, Open FPGA Design FlowRealistic Digitizer Application Example Phase & magnitude correction

SystemVue, Open FPGA Design FlowRequired Hardware: M9703 with FDK option to

SystemVue, Open FPGA Design FlowDemo II Setup Guide (…What We Did) Live

SystemVue, Open FPGA Design FlowDemo II Setup Guide (…What We Did) Live

SystemVue, Open FPGA Design FlowRealistic Digitizer Application Example Phase & magnitude correction

Demo II Setup Guide SystemVue Design – Signal Imbalance CorrectionSystemVue, Open

SystemVue, Open FPGA Design FlowDemo II Setup Guide SystemVue Design –

Demo II Setup Guide SystemVue Design – Chassis Configuration (+External Splitter)SystemVue, Open

Demo II Setup Guide SystemVue Design – M9703A ConfigurationSystemVue, Open FPGA Design

SystemVue, Open FPGA Design FlowDemo II Setup Guide SystemVue Design – 5

SW simulation step only (no HW)Source M8190 configurationM9703 measurement + calculate

Demo II Setup Guide Cosim Step 1 (no HW) – M9703A Target

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 1 (no

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 1 (no

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 1 (no

SW simulation step only (no HW)Source M8190 configurationM9703 measurement + calculate

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 2 –

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 2 –

M8190A Secondary Address 60005 (Cleared)SystemVue, Open FPGA Design FlowDemo II Setup

SystemVue, Open FPGA Design FlowM8190A Primary Address 127.0.0.1 (Error)M8190A Secondary Address

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 2 –

SW simulation step only (no HW)Source M8190 configurationM9703 measurement + calculate

M9703 Cosim ParametersM9703 Connection and OptionsSystemVue, Open FPGA Design FlowDemo II

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 3 –

Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) MagnitudeSystemVue,

Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) PhaseSystemVue,

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 3(1) –

SW simulation step only (no HW)Source M8190 configurationM9703 measurement + calculate

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 4 –

SW simulation step only (no HW)Source M8190 configurationM9703 measurement + calculate

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design FlowDefault Path (Error)User Path (Cleared)Note: Drive letter

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5 –

Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) MagnitudeSystemVue,

Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) PhaseSystemVue,

SystemVue, Open FPGA Design FlowDemo II Setup Guide Cosim Step 5(1) –

SummaryIntroduction to SystemVue hardware design kitGeneral SystemVue hardware design flowIntegrated FPGA

Thank you Questions yahia_tachwali@keysight.comSystemVue/FPGA Flow

Hardware Design Using SystemVue
SystemVue, Open FPGA Design Flow
HDL Files
IP
Graphical Design Entry
Textual/Binary

SystemVue Hardware Design Kit Model based graphical design tool
Predict hardware behaviors, before

PART I: SystemVue Open FPGA Design Flow
SystemVue, Open FPGA Design Flow

SystemVue FPGA Design Flow
SYSTEM LEVEL
SystemVue, Open FPGA Design Flow

Various fixed point blocks for hardware design
symbol mapping
1st half
band filtering
CIC
filter
CORDIC
modulator
phase accumulator
2nd

Design Optimization
Fixed Point Analysis
Sweep Analysis
Recursive Graphical Design
Design1
Design1
Design1
Design1
Design1
SystemVue, Open FPGA Design Flow

Demo One SystemVue general FPGA design flow
Native simulation
HDL co-simulation
HIL co-simulation
Hardware

PART II: Integrated Design Flow for M9703A Digitizer
SystemVue, Open FPGA Design

Integrated Hardware Design Flow for Digitizer
Realization of rapid real-time application development

Key Benefits of the integrated design flow
Early development of Firmware/Software APIs

Overview of M9703A High Speed Digitizer
SystemVue/FPGA Flow
8 phase-coherent channels (4 when

DPU FPGA user core ADC input format

1-Ch mode (3.2GS/s) 2-Ch

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

M9703A FPGA Design Flow
C++ simulation or C++/HDL mixed simulation if

M9703A FPGA Design Flow
SystemVue/FPGA Flow
Design entry and software simulation

M9703A FPGA Design Flow
SystemVue/FPGA Flow
Design entry and software simulation

M9703A FPGA Design Flow
SystemVue/FPGA Flow
Design entry and software simulation

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

M9703A FPGA Design Flow
M9703A FPGA programming file auto generation
SystemVue/FPGA Flow
Auto HDL

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

M9703A FPGA Design Flow
Design entry and software simulation
M9703A FPGA programming file

M9703A FPGA Design Flow
SystemVue/FPGA Flow
M9703A instrument co-simulation with SystemVue
M9703 Cosim Model
M9703

M9703A FPGA Design Flow
M9703A instrument co-simulation with SystemVue

M9703A FPGA Design Flow
M9703A instrument co-simulation with SystemVue

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
AD
DDC
FIR
W
Φ
∑
AD
DDC
FIR
W
Φ
AD
DDC
FIR
W
Φ
AD
DDC
FIR
W
Φ
Adaptive Algorithm
I
Q
BEAMS
FPGA
RF

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
What is

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
Signal processing
Trigger

Realistic Digitizer Application Example Phase & magnitude correction for multi-channel digitizer
Block diagram

SystemVue, Open FPGA Design Flow
Realistic Digitizer Application Example Phase & magnitude correction

SystemVue, Open FPGA Design Flow
Required Hardware:
M9703 with FDK option to

SystemVue, Open FPGA Design Flow
Demo II Setup Guide (…What We Did) Live

SystemVue, Open FPGA Design Flow
Demo II Setup Guide (…What We Did) Live

SystemVue, Open FPGA Design Flow
Realistic Digitizer Application Example Phase & magnitude correction

Demo II Setup Guide SystemVue Design – Signal Imbalance Correction
SystemVue, Open

SystemVue, Open FPGA Design Flow
Demo II Setup Guide SystemVue Design –

Demo II Setup Guide SystemVue Design – Chassis Configuration (+External Splitter)
SystemVue, Open

Demo II Setup Guide SystemVue Design – M9703A Configuration
SystemVue, Open FPGA Design

SystemVue, Open FPGA Design Flow
Demo II Setup Guide SystemVue Design – 5

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 1 (no

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 1 (no

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 1 (no

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 2 –

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 2 –

M8190A Secondary Address 60005 (Cleared)
SystemVue, Open FPGA Design Flow
Demo II Setup

SystemVue, Open FPGA Design Flow
M8190A Primary Address
127.0.0.1 (Error)
M8190A Secondary Address

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 2 –

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

M9703 Cosim Parameters
M9703 Connection and Options
SystemVue, Open FPGA Design Flow
Demo II

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 3 –

Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) Magnitude
SystemVue,

Demo II Setup Guide Cosim Step 3 – Reference Channel (In1) Phase
SystemVue,

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 3(1) –

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 4 –

SW simulation step only (no HW)
Source M8190 configuration
M9703 measurement + calculate

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design Flow
Default Path (Error)
User Path (Cleared)
Note: Drive letter

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5 –

Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) Magnitude
SystemVue,

Demo II Setup Guide Cosim Step 5 – Corrected Channel (In3) Phase
SystemVue,

SystemVue, Open FPGA Design Flow
Demo II Setup Guide Cosim Step 5(1) –

Summary
Introduction to SystemVue hardware design kit
General SystemVue hardware design flow
Integrated FPGA

Thank you Questions yahia_tachwali@keysight.com
SystemVue/FPGA Flow