P9X79 Series Confidential

Содержание

Слайд 2

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Communication BUS Introducing
Слайд 3

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 4

CPU 6C/12T, 4C/8T Support PCIe 3.0 DRAM support up to 4ch,

CPU 6C/12T, 4C/8T
Support PCIe 3.0
DRAM support up to 4ch, 8xDIMM, Max.

64GB
Supports NVIDIA® 3-Way SLI™ Technology Supports AMD Quad-GPU CrossFireX™ Technology
SATA 6G *2, SATA 3G *4
USB 2.0 *14
Remove SAS port
Слайд 5

Support 8GB,MAX is for 64GB Support DDR3 2400(O.C.)/2133(O.C.) 1866/1600/1333/1066 Support Intel®

Support 8GB,MAX is for 64GB
Support DDR3 2400(O.C.)/2133(O.C.)
1866/1600/1333/1066
Support Intel®

Extreme Memory
Profile(XMP)
Support DIGI+ Power Control
2 + 2 Phase Control
Слайд 6

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 7

Слайд 8

Слайд 9

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 10

DIGI+ Power Control (2/6) Most Precise Adjustment on CPU & DRAM

DIGI+ Power Control (2/6)
Most Precise Adjustment on CPU & DRAM
Extreme Performance

& O.C. Capability for CPU & DRAM
High System Stability

Digital Power : CPU + DRAM

Intelligent Digital
Power Controller (CPU)

Intelligent Digital
Power Controller (DRAM)

Слайд 11

Smart chip control without boot-up No need to open chassis Complete within only ONE click

Smart chip control
without boot-up

No need to
open chassis

Complete within
only

ONE click
Слайд 12

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 13

DRAM power control: Analog ? DIGITAL Clock Generator: PCH Internal ?

DRAM power control: Analog ? DIGITAL
Clock Generator: PCH Internal ? External


E-SATA support 6G ? Asmedia1061

X79 is native support PCIe 3.0
BIOS can park setting on gen2 or gen3 for compatibility.

Слайд 14

Analog PWM CONTROLLER UP6203 1.5VDUAL_REF EC phase MOS driver 1.5VDUAL Digital

Analog
PWM CONTROLLER
UP6203

1.5VDUAL_REF

EC

phase

MOS
driver

1.5VDUAL

Digital
PWM CONTROLLER
ASP1101

EC

phase

MOS
driver

1.5VDUAL

CPU

SMBus

SVID

P9 series DRAM power control

P8 series DRAM

power control
Слайд 15

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 16

Слайд 17

ICS428: SIO, PCI, SATA… ICS1218: CPU, CPU_QPI, DMI, PCIE, PCIE onboard device… ICS1218

ICS428:
SIO, PCI, SATA…

ICS1218:
CPU, CPU_QPI,

DMI,
PCIE, PCIE onboard
device…

ICS1218

Слайд 18

PCIE2.0 USB

PCIE2.0

USB

Слайд 19

1218 428 +VTT_CPU_PWRGD CK420_PWRGD# 25 MHz 25 MHz Power Power

1218

428

+VTT_CPU_PWRGD

CK420_PWRGD#

25 MHz

25 MHz

Power

Power

Слайд 20

+3VDUAL +VDD_CLK

+3VDUAL

+VDD_CLK

Слайд 21

428 CLK GEN 1218 CLK GEN

428 CLK GEN

1218 CLK GEN

Слайд 22

Слайд 23

Server MB (For C_CPU) SAS Marvall 9128 (SATA) C_PCH_GND (ex: E-SATA)

Server MB (For C_CPU)

SAS

Marvall 9128
(SATA)

C_PCH_GND
(ex: E-SATA)

Слайд 24

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 25

Слайд 26

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Слайд 28

Слайд 29

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 30

G3: Battery S0: All Power S3: Standby and Dual Deep S5: Only ATX Power

G3: Battery S0: All Power S3: Standby and Dual Deep S5: Only ATX Power

Слайд 31

(PWRBTN#IN, KB MS Wakeup)

(PWRBTN#IN, KB MS Wakeup)

Слайд 32

Слайд 33

SIO 3V_ATX +BAT_3V SR88 S_SRTCRST O2_ECRST# Power Supply O_RSMRST# O2_ECRST# O_RSMRST#

SIO

3V_ATX

+BAT_3V

SR88

S_SRTCRST

O2_ECRST#

Power Supply

O_RSMRST#

O2_ECRST#

O_RSMRST#

O2_RSMRST#

1

2

3

4

5

6

Слайд 34

O2_ECRST# O2_RSMRST# P_+VCCPLL_REF +1.8V level (0.03V in S5) P_+VTTCPU_REF +1.05V level

O2_ECRST#

O2_RSMRST#

P_+VCCPLL_REF +1.8V level (0.03V in S5)

P_+VTTCPU_REF +1.05V level (0.8V in S5)

P_+1.1V_SB_REF +1.1V level

P_+VTTDDR_AB_REF_10 +0.75V

level

P_+1.5V_SB_REF_10 +1.5V level

P_+VTTDDR_CD_REF_10 +0.75V level

O_RSMRST#

O2_CUT_PSON#

O_PSON#

O2_PSON#

+3V level

+3V level

8

6

7

Слайд 35

SIO Power Button O_PWRBTN#IN O_PWRBTN# SIO SLP_S3# SLP_S4# O_PSON# O2_CUT_PSON# O2_PSON#

SIO

Power Button

O_PWRBTN#IN

O_PWRBTN#

SIO

SLP_S3#
SLP_S4#

O_PSON#

O2_CUT_PSON#

O2_PSON#

+3V level

+3V level

+3V level

+5V level

Power Supply

O2_PSON#

3V, 5V, 12V

Power Supply

B_ATX_PWROK

SIO

+3V level

+5V

level

10

9

11

12

13

13

14

15

Слайд 36

+VTT_CPU, +1.5VDUAL_AB, +1.5VDUAL_CD, +1.1V_SB, +1.5V_SB +1.05V level +1.5V level +1.5V level

+VTT_CPU, +1.5VDUAL_AB, +1.5VDUAL_CD, +1.1V_SB, +1.5V_SB

+1.05V level

+1.5V level

+1.5V level

+1.1V level

+1.5V level

16

+VDDQ_AB_PWRGD
S_DRAMPWROK

+VDDQ_CD_PWRGD
S_DRAMPWROK

H_DRAMPWROK_AB

H_DRAMPWROK_CD

17

IC

SR1478

+1.5VDUAL_CD

+VTT_CPU

18

MB

Logic Circuit

+VTT_CPU_PWRGD

+1.5V level

+3V level

Слайд 37

+VTTCPU => VTT_CPU_PWRGD

+VTTCPU => VTT_CPU_PWRGD

Слайд 38

19 +VTT_CPU_PWRGD VCORE IC VCCSA IC SR151 SR1003 P_VCORE_EN_10 P_VCCSA_EN_10 SR255

19

+VTT_CPU_PWRGD

VCORE
IC

VCCSA
IC

SR151

SR1003

P_VCORE_EN_10

P_VCCSA_EN_10

SR255

Clock Gen

MB Logic Circuit

20

21

VCORE
IC

VCCSA
IC

P_VCORE_EN_10

P_VCCSA_EN_10

+VCORE

+VCCSA

(Around +1V)

Слайд 39

VCORE IC P_VCORE_VRDY_6 22 O2_GPI1 MB Logic Circuit O2R64 S_VRMPWRGD EC

VCORE
IC

P_VCORE_VRDY_6

22

O2_GPI1

MB Logic Circuit

O2R64

S_VRMPWRGD

EC

O2_GPO1

SR535

O2_GPO1

+VSA_CPU_PWRGD

VCORE
IC

MB Logic Circuit

P_+VCCPLL_REF_R_10

23

P_+VCCPLL_REF_R_10

VCCPLL
IC

+VCCPLL

+1.8V level

Слайд 40

X 1 2 3 3 EC 5 4 5 6

X

1

2

3

3

EC

5

4

5

6

Слайд 41

+VSA_CPU_PWRGD => P_+VCCPLL_REF_R_10

+VSA_CPU_PWRGD => P_+VCCPLL_REF_R_10

Слайд 42

24 SIO O_PWROK_SIO EC SR1478 O_PWROK H_CPUPWRGD H_SID_CLK H_SID_DATA H_SID_ALERT# VCORE

24

SIO

O_PWROK_SIO

EC

SR1478

O_PWROK

H_CPUPWRGD

H_SID_CLK

H_SID_DATA

H_SID_ALERT#

VCORE
IC

25

+3V level

+1.05V level

+1.05V level

Слайд 43

S_VRMPWRGD 26 S_PLTRST# SIO LAN Other Devices 27 SIO O_PCIRST#_PCIEX16_* [1:3]

S_VRMPWRGD

26

S_PLTRST#

SIO

LAN

Other Devices

27

SIO

O_PCIRST#_PCIEX16_* [1:3]

MB PCIE

S_PLTRST#

28

H_CPURST#

+3V level

+3V level

+1.05V level

Слайд 44

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 45

S_PLTRST => H_CPURST# 1 EC 2 3

S_PLTRST => H_CPURST#

1

EC

2

3

Слайд 46

EC is a 8051 micro-processor EC functions DIGI+ Power Control--SMBUS interface

EC is a 8051 micro-processor
EC functions
DIGI+ Power Control--SMBUS interface
Over-voltage control,

3.2V/512=6.25mV/step--PWM interface
Voltage sense--ADC interface
TPU, EPU & EUP Control --GPIO interface
Memory OK--GPIO interface
PWM Fan Control--PWM & Fan-in interface
SIO & PCH -- LPC interface
BIOS
Слайд 47

Слайд 48

USB Back up Condition USB Type : FAT32、FAT type BIOS Image

USB Back up Condition
USB Type : FAT32、FAT type
BIOS Image : Follow

X79 each Model Crash free naming(EX: X79 DLX: P9X79D.ROM、X79 PRO: P9X79PRO.ROM…)
Слайд 49

According these signals connecting to EC, EC can realize present system status

According these signals connecting to EC, EC can realize present system

status
Слайд 50

Слайд 51

USB Device Default : SB to USB SPI to SB 1

USB Device

Default : SB to USB
SPI to SB

1

Слайд 52

USB Device At S5 status, press Backup button more than 3

USB Device

At S5 status, press Backup button more than 3 sec

to start back function.

2

1

Слайд 53

USB Device 2 1 3 3 2

USB Device

2

1

3

3

2

Слайд 54

USB Device Confirm ROMID & MODELID and others information are normal 1 3 3 2 4

USB Device

Confirm ROMID & MODELID and others information are normal

1

3

3

2

4

Слайд 55

1 3 3 2 4 5 5

1

3

3

2

4

5

5

Слайд 56

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Слайд 60

When System BIOS update EC Firmware EC Broken status: EC flash

When System BIOS update EC Firmware
EC Broken status:
EC flash is corrupted


The data in the EC or EC flash might be corrupted.
Please contact ASUS Technical Support for help
EC flash update fail
The data in the EC or EC flash might be corrupted.
Please contact ASUS Technical Support for help
Слайд 61

Power & Reset & XTAL: 24 MHz Crystal

Power & Reset & XTAL:

24 MHz Crystal

Слайд 62

O2_OP_mode: This PIN is used for RD & factory to update

O2_OP_mode:
This PIN is used for RD & factory to update EC

firmware or flash programming.
Normal should always keep low.
Слайд 63

O2_PWM0~5:

O2_PWM0~5:

Слайд 64

O2_GPO2~3: Load default -> check status : (1，1) X79 series models

O2_GPO2~3:
Load default -> check status : (1，1)
X79 series models use these

two pins to control BLK frequency

BCLK

Слайд 65

O2_GPI1 & O2_GPO1: Correct: O2_GPI1:H & O2_GPO1:H J_SILENT#(PROCHOT#): If this pin

O2_GPI1 & O2_GPO1:
Correct: O2_GPI1:H & O2_GPO1:H
J_SILENT#(PROCHOT#):
If this pin of

X79 series model is pulled low at S5, it can’t boot up.
Слайд 66

O_PWRBTN#IN_R& O_RSTCON#: Can’t Keep Low O2_CUT_PSON#: To keep PWRBTN motion AC

O_PWRBTN#IN_R& O_RSTCON#: Can’t Keep Low
O2_CUT_PSON#: To keep PWRBTN motion
AC Power

On -> PWM signal ready -> O2_CUT_PSON#: H
When starting to USB BIOS flashback, this pin is also low.
Слайд 67

SMBUS & O2_SMB_SWITCH: Hang”0d0c” : EC check internal register setting of each DIGI+ Power Control.

SMBUS & O2_SMB_SWITCH:
Hang”0d0c” : EC check internal register setting of

each DIGI+ Power Control.
Слайд 68

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 69

33MHz LPC Interface PECI Platform Environment Control Interface SMBus H/W Monitor

33MHz

LPC Interface

PECI
Platform Environment Control Interface

SMBus

H/W Monitor

PORT 80

Deep S5

KBMS

ACPI
Advanced Configuration and Power

Interface

GPIO

COM1

FAN OUT

PCH

RSTOUT

New CPU

48MHz

Clock Gen

3.3V

Power

Слайд 70

Слайд 71

ASP1000 and ASP1101 are all DIGI power controller, all BIOS setting

ASP1000 and ASP1101 are all DIGI power controller, all BIOS setting

function can transmit signals through SMBUS to change or adjust IC internal value and in order to get all DIGI VRM function.
Слайд 72

Vcc=3.3V Vinsen = 0.86V VRHot = Vcc EN=3.3V The Sequence: VCC->Vinsen->VRHot->EN

Vcc=3.3V
Vinsen = 0.86V
VRHot = Vcc
EN=3.3V

The Sequence:
VCC->Vinsen->VRHot->EN

Others Signals:
VSEN (FB+)
RRES
V18A
VR_READY
PIN17~19
SMBus
PWM signal

7.5 K Ohm

ASP1000

Слайд 73

Vcc=3.3V Vinsen = 0.86V VRHot = Vcc EN=3.3V The Sequence: VCC->Vinsen->VRHot->EN ASP1101 7.5 K Ohm

Vcc=3.3V
Vinsen = 0.86V
VRHot = Vcc
EN=3.3V

The Sequence:
VCC->Vinsen->VRHot->EN

ASP1101

7.5 K Ohm

Слайд 74

Vcc=3.3V Vinsen = 0.38V VRHot = 3VSB EN=1V The Sequence: VCC->Vinsen->VRHot->EN 7.5 K Ohm ASP1101

Vcc=3.3V
Vinsen = 0.38V
VRHot = 3VSB
EN=1V

The Sequence:
VCC->Vinsen->VRHot->EN

7.5 K Ohm

ASP1101

Слайд 75

When the debug card shows 00, the CPU or sequence can’t

When the debug card shows 00, the CPU or sequence can’t

run completely.
(1) Visually inspect: (wrong parts, components missing …)
(2) Measure the impedance (component solder on the board)     A. The impedance of each power circuit is short with GND or not.     B. Each MOS, the impedance of the H-S or L-S MOS GS side is K level,     C. the impedance of DS side can’t be zero     D. Compare the difference with a golden compare .
(3) Power on and check each voltage
Слайд 76

Step 1: Multi-meter in Ω level : “+” side connects with

Step 1: Multi-meter in Ω level : “+” side connects with Source,

“-” side connects with Gate. Let MOSFET going into the cut-off state. Step 2: Multi-meter in diode level : “+” side connects with Source, “-” side connects with drain, measure Vf: 0.3V ~ 0.6V Step 3: Multi-meter in resistance level :
“+” side connects with drain, “-” side connects with source Value: xM Ω, ~ ∞ Ω, “+” side connects with drain, “-” side connects with gate Value: xM Ω, ~ ∞ Ω
“+” side connects with source, “-” side connects with gate Value: xM Ω, ~ ∞ Ω Step 4:
Multi-meter in resistance level : “+” side connects with gate, “-” side connects with source ,to turn on MOSFET “+” side connects with drain, “-” side connects with source Value: 0Ω ~~ 10 Ω
Слайд 77

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 78

Controlling from EC VIN Control PIN REF VOUT Power: 1. 3V 2. +VCCPLL_1 3. +VCCPLL


Controlling from EC

VIN
Control PIN
REF
VOUT

Power:
1. 3V
2. +VCCPLL_1
3. +VCCPLL

Слайд 79

VIN Control PIN REF VOUT UP0109 GND GND 3V 0 ohm


VIN
Control PIN
REF
VOUT

UP0109

GND

GND

3V

0
ohm

5V

P_+1.5V_SB_REF_10

4

8

1.5V_SB

Power:
3V => +1.5V_SB

Слайд 80

+d

+d

Слайд 81

SIO PR217 P_+VTTCPU_FB_R1_10 O_+VTTCPU_OV# Power: 12V=>+VTTCPU

SIO

PR217

P_+VTTCPU_FB_R1_10

O_+VTTCPU_OV#

Power:
12V=>+VTTCPU

Слайд 82

5V

5V

Слайд 83

0 SIO PR527 P_+1.1V_SB_FB_R1_10 O_+1.1V_SB_OV#

0

SIO

PR527

P_+1.1V_SB_FB_R1_10

O_+1.1V_SB_OV#

Слайд 84

Intel X79 Platform Structure P9X79 Series Architecture New Feature Difference With

Intel X79 Platform Structure
P9X79 Series Architecture
New Feature
Difference With P8 Series
Clock

Distribution
Power Flow & Critical Power on X79 Platform
Power Sequence
Embedded Controller Introducing
SIO and Other Power Chipset Introducing
Power theory and working condition
Communication BUS Introducing
Слайд 85

VCORE VTTCPU VSA_CPU VCCPLL 1.5VDUAL_CD 1.5VDUAL_AB C_CPU C_CPU# C_CPU_QPI C_CPU_QPI# H_CPUPWRGD

VCORE
VTTCPU
VSA_CPU
VCCPLL
1.5VDUAL_CD
1.5VDUAL_AB

C_CPU
C_CPU#
C_CPU_QPI
C_CPU_QPI#

H_CPUPWRGD
H_CPURST#

3V
3VSB
1.1V_SB
1.5V_SB
1.1V_SB_VCCDMIPLL

C_PCH_DMI
C_PCH_DMI#
32.768 Hz

O_PWROK
S_VRMPWRGD
S_PLTRST#

DMI_ZCOMP

DMIRBIAS

Слайд 86

H_DMI_TXP[3:0] H_DMI_TXN[3:0] H_DMI_RXP[3:0] H_DMI_RXN[3:0]

H_DMI_TXP[3:0]

H_DMI_TXN[3:0]

H_DMI_RXP[3:0]

H_DMI_RXN[3:0]

Слайд 87

3V 3VSB 1.1V_SB 1.5V_SB C_PCH_14M 32.768 Hz O_PWROK S_VRMPWRGD S_PLTRST# 3V_SPI

3V
3VSB
1.1V_SB
1.5V_SB

C_PCH_14M
32.768 Hz

O_PWROK
S_VRMPWRGD
S_PLTRST#

3V_SPI (3VSB)
F1_SPI_HOLD#
O_BIOS_WP#

5VSB
O2_SPI_SWITCH
(From EC)

Слайд 88

O2_SPI_SWITCH (From EC)

O2_SPI_SWITCH
(From EC)

Слайд 89

VCORE VTTCPU VSA_CPU VCCPLL 1.5VDUAL_CD 1.5VDUAL_AB H_DRAMVREFDQ_TX_CD H_DRAMVREFDQ_TX_AB H_DRAMVREFDQ_RX_CD H_DRAMVREFDQ_RX_AB H_DDR_CD_1V05_SDA

VCORE
VTTCPU
VSA_CPU
VCCPLL
1.5VDUAL_CD
1.5VDUAL_AB

H_DRAMVREFDQ_TX_CD
H_DRAMVREFDQ_TX_AB
H_DRAMVREFDQ_RX_CD
H_DRAMVREFDQ_RX_AB
H_DDR_CD_1V05_SDA
H_DDR_AB_1V05_SDA
H_DDR_CD_1V05_SCL
H_DDR_AB_1V05_SCL
H_DRAMPWROK_CD
H_DRAMPWROK_AB
D3_MEMHOT#_AB
D3_MEMHOT#_CD

3V
1.5VDUAL_CD
1.5VDUAL_AB
+VTTDDR_AB
+VTTDDR_CD
D3_VREFDQ_A~D
D3_VREFCA_A~D

D3_M[A~D]_CLK[3:0]
D3_M[A~D]_CLK#[3:0]

D3_RESET#AB
D3_RESET#CD

H_DDR_CD_3V3_SDA
H_DDR_AB_3V3_SCL
H_DDR_CD_3V3_SDA
H_DDR_AB_3V3_SCL

Слайд 90

D3_DQ_A[64:0] D3_DQS_A[7:0] D3_DQS_A#[3:0] A~D A~D

D3_DQ_A[64:0]

D3_DQS_A[7:0]

D3_DQS_A#[3:0]

A~D

A~D

Слайд 91

3V 3VSB 1.1V_SB 1.5V_SB C_PCH_14M C_PCI_PCH 32.768 Hz O_PWROK S_VRMPWRGD S_PLTRST#

3V
3VSB
1.1V_SB
1.5V_SB

C_PCH_14M
C_PCI_PCH
32.768 Hz

O_PWROK
S_VRMPWRGD
S_PLTRST#

SIO

3V
3VSB_ATX
VTTCPU

C_48M_SIO
C_PCI_SIO

O_PWROK_SIO
S_PLTRST#

Слайд 92

F_SERIRQ# F_LAD[3:0]

F_SERIRQ#

F_LAD[3:0]

- Предыдущая
Математическое моделирование
Следующая -
Дискретная случайная величина

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