High-Density Ac-Dc Power Supplies using Active-Clamp Flyback Topologу

Содержание

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Agenda Introduction to active-clamp flyback operation (ACF) ACF light-load efficiency challenge

Agenda

Introduction to active-clamp flyback operation (ACF)
ACF light-load efficiency challenge
Introduction to the

NCP1568 – Ac-Dc ACF PWM IC.
Light load and standby solution
Design equations for transformer selection of the ACF
Primary and secondary component selection considerations
Performance data of ultra-high density active-clamp flyback board.
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Introduction to Active-Clamp Flyback Operation (ACF)

Introduction to Active-Clamp Flyback Operation (ACF)

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Active-Clamp Flyback The clamp diode in a standard flyback converter is

Active-Clamp Flyback

The clamp diode in a standard flyback converter is replaced

by a switch
hence the name Active-Clamp Flyback or ACF.

Standard Flyback Converter w. RCD clamp

Active-Clamp Converter

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Why Active-Clamp Flyback? Zero-Volt Switching of the FETs with Fixed-Switching Frequency

Why Active-Clamp Flyback?

Zero-Volt Switching of the FETs with Fixed-Switching Frequency
Results in

high switching frequency, improves efficiency and EMI.
Soft Increase in Secondary Current
Good for EMI
Clean Drain Waveforms Without Any Ringing
Better efficiency as the leakage energy is recycled.
Better EMI
Single-Ended Topology
Relatively simple design of magnetics compared to LLC.
Single switch/diode in the secondary.
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Energy-Storage Mode The energy-storage mode is similar to that of a

Energy-Storage Mode

The energy-storage mode is similar to that of a classical

flyback converter: when the main FET is on, energy is stored in the transformer.

ACF works in continuous conduction mode. Its input-to-output relationship is given by:

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Transition from Energy-Storage Mode to Power-Delivery Mode When FET turns off,

Transition from Energy-Storage Mode to Power-Delivery Mode

When FET turns off, the

lump capacitor on the SW node is linearly charged at a rate given by Tcharge
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Power-Delivery Mode In this mode, Lleak resonates with clamp capacitor (Cclamp).

Power-Delivery Mode

In this mode, Lleak resonates with clamp capacitor (Cclamp). The

resonant frequency is given by:

The primary resonant current is given by:

The magnetizing current during the (1-D) phase is given by:

The difference between the primary resonant current and the magnetizing current flows in the secondary

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Transition from Power-Delivery Mode to Energy-Storage Mode When the clamp FET

Transition from Power-Delivery Mode to Energy-Storage Mode

When the clamp FET

turns off, Lleak resonates with Cclamp. For the main FET to get ZVS, following condition has to be satisfied
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Leakage Inductance Needed for ZVS For universal design, leakage inductance needed

Leakage Inductance Needed for ZVS

For universal design, leakage inductance needed

to get ZVS increases in a parabolic fashion.
Increasing leakage & tightly controlling the spread add cost
Additional resonant inductor is an alternative, but inductor adds cost & volume

Assuming Clump = 220 pF, constant Ipeak = 1 A,
85 V to 265 V rms (universal input)

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ZVS Phenomenon – 1 During Tdis1 (shaded region), Lleak resonates with

ZVS Phenomenon – 1

During Tdis1 (shaded region),
Lleak resonates with Cclamp.


The time it takes for the resonance between leakage inductance and lump capacitance to reach its valley point is 1/4th of a resonant period. Therefore:
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ZVS Phenomenon – 2 During Tdis2 (shaded region), negative magnetizing current

ZVS Phenomenon – 2

During Tdis2 (shaded region), negative magnetizing current starts

to discharge the clamp capacitance
The time it takes to discharge the lump capacitance is given by:
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Fixed-Frequency Operation Magnetizing current in ACF is in CCM. As the

Fixed-Frequency Operation

Magnetizing current in ACF is in CCM.
As the load current

decreases, the valley point of the magnetizing current decreases.
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Variable-Frequency Operation As the load current decreases, increasing the frequency minimizes

Variable-Frequency Operation

As the load current decreases, increasing the frequency minimizes Imag

and reduces the conduction losses.
Ideally, the valley of the magnetizing current needs to be maintained constant for ZVS.
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Light-Load Efficiency & Standby Power Challenge

Light-Load Efficiency & Standby Power Challenge

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Light-Load Efficiency Requirements European Code of Conduct, Ver. 5, Tier 2

Light-Load Efficiency Requirements

European Code of Conduct, Ver. 5, Tier 2 poses

stringent efficiency standards at light-load condition

For a 60-W design, 4-point average (25%, 50%, 75%, and 100% average) efficiency needs to be > 88% for full load and 78% for 10% load.

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Standby Power Standard US DoE standards are equally stringent Most of

Standby Power Standard

US DoE standards are equally stringent
Most of the brand

name OEMs require to pass
stringent Tier-2 standard

DoE: Department of Energy

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ACF Specific Light-Load Challenges Magnetizing current is in CCM. Frequency modulation

ACF Specific Light-Load Challenges

Magnetizing current is in CCM.
Frequency modulation results in

high-frequency operation at light load
Classical frequency foldback is not possible to implement when magnetizing current is in CCM
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DCM Operation Holding active-clamp FET off, DCM operation can be implemented

DCM Operation

Holding active-clamp FET off, DCM operation can be implemented in

ACF.
This allows magnetizing current to enter DCM: frequency foldback can be implemented
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Introduction to NCP1568 Ac-Dc PWM Controller for ACF

Introduction to NCP1568

Ac-Dc PWM Controller for ACF

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Introduction to NCP1568 Control Scheme Adaptive ZVS frequency modulation allows variable

Introduction to NCP1568

Control Scheme
Adaptive ZVS frequency modulation allows variable Vout operation
Integrated

adaptive dead-time
Peak-current-mode control
DCM & Light-Load Operation
Optional transition to DCM mode
Frequency foldback with 31-kHz minimum frequency clamp
Quiet skip eliminates audible noise
Standby power < 30 mW
HV Startup
700-V HV startup JFET
Integrated sensing of HV SW node for optimum ZVS
Brownout and X2 discharge inbuilt.
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Frequency Movement vs. Load NCP1568 NCP1568 features a combination of nonlinear

Frequency Movement vs. Load

NCP1568

NCP1568 features a combination of nonlinear & linear

foldback schemes
The lower the frequency at light load, the higher the efficiency
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Clamp Capacitor Challenge VCLAMP_DCM>VCLAMP_ACF Leakage energy is not recycled in DCM

Clamp Capacitor Challenge

VCLAMP_DCM>VCLAMP_ACF
Leakage energy is not recycled in DCM and is

dissipated in the clamp resistor (RClamp)
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Transition from DCM to ACF Active-clamp FET can be soft-started to

Transition from DCM to ACF

Active-clamp FET can be soft-started to discharge

the clamp capacitor slowly.
Leading-edge modulation of active-clamp FET allows the main FET to achieve ZVS
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DCM Operation Determination NCP1568 can be configured to operate in pure

DCM Operation Determination

NCP1568 can be configured to operate in pure ACF

mode and pure DCM mode.
Efficiency can be plotted in both ACF and DCM to determine optimal transition points.
NCP1568 uses the feedback information to transition from ACF to DCM or vice-versa.
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Key Components Selection Transformer Design & Key Equations

Key Components Selection

Transformer Design & Key Equations

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Design Specifications

Design Specifications

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Turns Ratio Selection Turns ratio can be calculated by the following

Turns Ratio Selection

Turns ratio can be calculated by the following formula

assuming Dmax=0.5.

Turns ratio should be calculated at the lowest input voltage while delivering maximum power
For this design, rounded turns ratio is 6.

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Minimum On-Time Minimum on-time needs to be calculated at worst case

Minimum On-Time
Minimum on-time needs to be calculated at worst case duty

ratio to ensure that the controller can deliver the pulses

NCP1568 has a minimum on-time of 200 ns. The calculated on-times of the above equations are 600 ns and 700 ns respectively.
If the min on-time is < 200 ns, the turns ratio needs to be adjusted and the process iterated

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Valley Current for ZVS In order to determine the inductance value,

Valley Current for ZVS

In order to determine the inductance value, valley

current is needed.
To calculate the valley current, the capacitance lumped at the SW node can be expressed as follows:

Main FET
Output capacitance

Active Clamp FET
Output capacitance

Synchronous Rectifier FET

The above capacitances can be approximated from the FET datasheet.
Considering an ac-dc power supply, a 600-V FET for primary and a 120-V type for secondary have been selected resulting in a Clump of 220 pF

Co(er) is the nonlinear capacitance averaged along a given ΔVDS

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Inductance Calculation Inductance can be calculated as follows: Where Dmin is

Inductance Calculation

Inductance can be calculated as follows:

Where Dmin is the minimum

duty cycle given by:

For this design, the above formula results in a magnetizing inductance of 120 µH

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Inductance vs. Required Valley Current for ZVS As the required valley

Inductance vs. Required Valley Current for ZVS

As the required valley current

for ZVS decreases, the inductance falls.
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Core Selection Assuming a 200-mT Bmax operating at 400 kHz results

Core Selection

Assuming a 200-mT Bmax operating at 400 kHz results in

a core loss of 1.8 W.

A RM8LP core has been selected for this low-profile and high-density design.

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Primary and Secondary Turns The primary and secondary turns can be

Primary and Secondary Turns

The primary and secondary turns can be calculated

from the following formulae:

This results in a primary turns of 23.
Since turns ratio is 6, 24 turns are selected for primary turns and 4 for secondary turns
A flux density, ∆B, of 0.2 T & Ae of 65 mm2 have been assumed for this design.

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Clamp Capacitor Selection Clamp capacitor should be selected at worst-case off-time

Clamp Capacitor Selection

Clamp capacitor should be selected at worst-case off-time i.e.,

lowest frequency and minimum D
Clamp capacitor should be selected such that it resonates 1/4th of the resonant period at worse case off-time.
Ceramic capacitors are selected for clamp capacitors. Standard derating should be followed (voltage and rms current).

The above equation results in 330 nF.
After derating, a 660 nF is selected

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RMS Current Formulae The primary and secondary FET selection criterion is

RMS Current Formulae

The primary and secondary FET selection criterion is no

different than with standard flybacks.
The active-clamp FET voltage rating is same as main FET.
The clamp and secondary FETs see different current waveforms than standard flyback. Their formulae are noted below
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60-W UHD-Board Performance

60-W UHD-Board Performance

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Simplified Schematic Secondary side is similar to any standard flyback topology.

Simplified Schematic

Secondary side is similar to any standard flyback topology.

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Frequency Modulation w. Load As the load current decreases, the negative

Frequency Modulation w. Load

As the load current decreases, the negative current

is minimized & kept constant leading to low conduction losses

2.25 A

1.7 A

1 A

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Fixed Frequency vs. Frequency Modulation 115 V rms, 1.5-A load Fixed

Fixed Frequency vs. Frequency Modulation

115 V rms, 1.5-A load
Fixed Fsw

of 231 kHz

115 V rms, 1.5-A load
Frequency modulation, Fsw = 260 kHz

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Frequency Movement w. Vout & Vin Frequency movement is similar to

Frequency Movement w. Vout & Vin

Frequency movement is similar to QR

flyback switching in 1st valley

90 V rms

265 V rms

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Frequency vs. Load Current Active-Clamp Mode Discontinuous Mode

Frequency vs. Load Current

Active-Clamp Mode

Discontinuous Mode

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DCM SW waveforms 90 V rms 265 V rms

DCM SW waveforms

90 V rms

265 V rms

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NCP1568 USB PD 65-W UHD Demonstration Board Featured Devices: NCP1568 ACF

NCP1568 USB PD 65-W UHD Demonstration Board

Featured Devices: NCP1568 ACF Controller

NCP51530 Half-Bridge Driver
NCP4305 SR Controller
Full Load Efficiency: 93.4% @ 115 V rms (20 V/3.0 A)
93.6% @ 230 V rms (20 V/3.0 A)
Transformer Type: RM8 LP
Power Density: 30 W/in3 or 17 W/cm3
Board Dimensions: 1.66” x 1.78” x 0.70” or
4.2 cm x 4.5 cm x 1.7 cm
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UHD Board Performance Achieving a full-load efficiency of 93.5% at a

UHD Board Performance

Achieving a full-load efficiency of 93.5% at a 60-W

output
Primary FETs running at 83 °C
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NCP1568 Demonstration Board Efficiency

NCP1568 Demonstration Board Efficiency