Содержание
- 2. To be covered today: Quick overview of the architectures of the both the Blackfin and Sharc
- 3. Sharc ADSP-21061[1]
- 4. Sharc’s Main Features[2]: 32/40-bit IEEE floating-point math 32-bit fixed-point MACs with 64-bit product and 80-bit accumulation
- 5. Sharc’s Main Features Cont.: Six nested levels of zero-overhead looping in hardware Four busses to memory
- 6. Blackfin ADSP-21535[3]
- 7. Blackfin’s Main Features[4]: Two 16-bit MACs, two 40-bit ALUs, and four 8-bit Video ALUs Support for
- 8. Blackfin’s Main Features Cont.: Possibility of the following parallel operations processed in one clock cycle Execution
- 9. Main Differences: The Blackfin is only a 16-bit integer processor, however can operate on 32-bit data
- 10. Main Differences Cont.: The Blackfin has 4 address registers (with corresponding base, length, and modify) to
- 11. Blackfin FIR Code Sample[5]: LSETUP(E_FIR_START,E_FIR_END) LC0=P1>>1; //Loop 1 to Ni/2 E_FIR_START: R1=PACK(R1.H,R0.H) || [I0++]=R0 || R2.L=W[I2++];
- 12. Benchmarks: For the Sharc[6] For the Blackfin[7]
- 13. Analysis: Blackfin is faster for the three algorithms Unsure of exact performance gain on the FFT
- 14. References ENCM515 Lecture Slides for January 11, 2002, [http://www.enel.ucalgary.ca/People/Smith/2002webs/encm515_02/02presentations/02january/02overviewSHARCarchitecture.ppt], Dr. Mike Smith Sharc Architecture Overview, [http://www.analog.com/technology/dsp/Sharc/architecture.html],
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