Interconnect delay. (Chapter 7)

Содержание

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Chapter 7 Interconnect Delay 7.1 Elmore Delay 7.2 High-order model and

Chapter 7 Interconnect Delay

7.1 Elmore Delay
7.2 High-order model and moment matching
7.3

Stage delay calculation
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Basic Circuit Analysis Techniques Output response Basic waveforms Step input Pulse

Basic Circuit Analysis Techniques

Output response
Basic waveforms
Step input
Pulse input
Impulse Input
Use simple input

waveforms to understand the impact of network design

Network structures & state

Input waveform & zero-states

Natural response vN(t)

(zero-input response)

Forced response vF(t)
(zero-state response)

For linear circuits:

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unit step function u(t)= 0 1 1 pulse function of width

unit step function

u(t)=

0

1

1

pulse function of width T

0

1/T

-T/2

T/2

unit impulse function

Basic Input Waveforms

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Definitions: (unit) step input u(t) (unit) step response g(t) (unit) impulse

Definitions:
(unit) step input u(t) (unit) step response g(t)
(unit) impulse input δ(t) (unit)

impulse response h(t)
Relationship
Elmore delay

Step Response vs. Impulse Response

(Input Waveform)

(Output Waveform)

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Analysis of Simple RC Circuit first-order linear differential equation with constant coefficients state variable Input waveform

Analysis of Simple RC Circuit

first-order linear differential
equation with
constant coefficients

state variable

Input
waveform

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Analysis of Simple RC Circuit zero-input response: (natural response) step-input response:

Analysis of Simple RC Circuit

zero-input response:

(natural response)

step-input response:

match initial state:

output response
for

step-input:
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Delays of Simple RC Circuit v(t) = v0(1 - e-t/RC) under

Delays of Simple RC Circuit

v(t) = v0(1 - e-t/RC) under step

input v0u(t)
v(t)=0.9v0 ⇒ t = 2.3RC v(t)=0.5v0 ⇒ t = 0.7RC
Commonly used metric TD = RC (Elmore delay to be defined later)
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Lumped Capacitance Delay Model R = driver resistance C = total

Lumped Capacitance Delay Model

R = driver resistance
C = total interconnect capacitance

+ loading capacitance
Sink Delay: td = R·C
50% delay under step input = 0.7RC
Valid when driver resistance >> interconnect resistance
All sinks have equal delay
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driver Lumped RC Delay Model Minimize delay ⇔ minimize wire length Rd Cload

driver

Lumped RC Delay Model
Minimize delay ⇔ minimize wire length

Rd

Cload

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Delay of Distributed RC Lines Vout(t) Vout(s) Laplace Transform R VIN

Delay of Distributed RC Lines

Vout(t)

Vout(s)

Laplace

Transform

R

VIN

VOUT

C

VOUT

VIN

R

C

0.5

1.0

VOUT

DISTRIBUTED

LUMPED

1.0RC

2.0RC

time

Step response of distributed and lumped RC

networks.
A potential step is applied at VIN, and the resulting VOUT
is plotted. The time delays between commonly used
reference points in the output potential is also tabulated.
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Delay of Distributed RC Lines (cont’d)

Delay of Distributed RC Lines (cont’d)

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Distributed Interconnect Models Distributed RC circuit model L,T or Π circuits

Distributed Interconnect Models

Distributed RC circuit model
L,T or Π circuits
Distributed RCL circuit

model
Tree of transmission lines
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Distributed RC Circuit Models

Distributed RC Circuit Models

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Distributed RLC Circuit Model (without mutual inductance)

Distributed RLC Circuit Model (without mutual inductance)

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Delays of Complex Circuits under Unit Step Input Circuits with monotonic

Delays of Complex Circuits under Unit Step Input

Circuits with monotonic response
Easy

to define delay & rise/fall time
Commonly used definitions
Delay T50% = time to reach half-value, v(T50%) = 0.5Vdd
Rise/fall time TR = 1/v’(T50%) where v’(t): rate of change of v(t) w.r.t. t
Or rise time = time from 10% to 90% of final value
Problem: lack of general analytical formula for T50% & TR!

t

1

0.5

v(t)

T50%

TR

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Delays of Complex Circuits under Unit Step Input (cont’d) Circuits with

Delays of Complex Circuits under Unit Step Input (cont’d)

Circuits with non-monotonic

response
Much more difficult to define delay & rise/fall time
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0.5 1 T50% v(t) t t v’(t) median of v’(t) (T50%)

0.5

1

T50%

v(t)

t

t

v’(t)

median
of v’(t)
(T50%)

Elmore Delay for Monotonic Responses

Assumptions:
Unit step input
Monotone output response
Basic

idea: use of mean of v’(t) to approximate median of v’(t)
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T50%: median of v’(t), since Elmore delay TD = mean of

T50%: median of v’(t), since
Elmore delay TD = mean of v’(t)

Elmore

Delay for Monotonic Responses
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Why Elmore Delay? Elmore delay is easier to compute analytically in

Why Elmore Delay?

Elmore delay is easier to compute analytically in most

cases
Elmore’s insight [Elmore, J. App. Phy 1948]
Verified later on by many other researchers, e.g.
Elmore delay for RC trees [Penfield-Rubinstein, DAC’81]
Elmore delay for RC networks with ramp input [Chan, T-CAS’86]
.....
For RC trees: [Krauter-Tatuianu-Willis-Pileggi, DAC’95] T50% ≤ TD
Note: Elmore delay is not 50% value delay in general!
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Elmore Delay for RC Trees Definition h(t) = impulse response TD

Elmore Delay for RC Trees

Definition
h(t) = impulse response
TD = mean of

h(t)
=

Interpretation
H(t) = output response (step process)
h(t) = rate of change of H(t)
T50%= median of h(t)
Elmore delay approximates the median of h(t) by the mean of h(t)

median
of v’(t)
(T50%)

h(t) = impulse response

H(t) = step response

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Elmore Delay of a RC Tree [Rubinstein-Penfield-Horowitz, T-CAD’83] Lemma: Proof: Apply

Elmore Delay of a RC Tree [Rubinstein-Penfield-Horowitz, T-CAD’83]

Lemma:

Proof:

Apply impulse func. at t=0:

imin

i

current

i→imin
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Elmore Delay in a RC Tree (cont’d) input i k j

Elmore Delay in a RC Tree (cont’d)

input

i

k

j

Si

path resistance Rii

Rjk

Theorem :

Proof

:
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Elmore Delay in a RC Tree (cont’d) We shall show later

Elmore Delay in a RC Tree (cont’d)

We shall show later on

that i.e. 1-vi(T) goes to 0 at a much faster rate than 1/T when T→∞
Let

(1)

vi(t)

1

0

t

area

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Some Definitions For Signal Bound Computation

Some Definitions For Signal Bound Computation

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Signal Bounds in RC Trees Theorem

Signal Bounds in RC Trees

Theorem

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Delay Bounds in RC Trees

Delay Bounds in RC Trees

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Computation of Elmore Delay & Delay Bounds in RC Trees Let

Computation of Elmore Delay & Delay Bounds in RC Trees

Let C(Tk)

be total capacitance of subtree rooted at k
Elmore delay
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Comments on Elmore Delay Model Advantages Simple closed-form expression Useful for

Comments on Elmore Delay Model

Advantages
Simple closed-form expression
Useful for interconnect optimization
Upper bound

of 50% delay [Gupta et al., DAC’95, TCAD’97]
Actual delay asymptotically approaches Elmore delay as input signal rise time increases
High fidelity [Boese et al., ICCD’93],[Cong-He, TODAES’96]
Good solutions under Elmore delay are good solutions under actual (SPICE) delay
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Comments on Elmore Delay Model Disadvantages Low accuracy, especially poor for

Comments on Elmore Delay Model

Disadvantages
Low accuracy, especially poor for slope computation
Inherently

cannot handle inductance effect
Elmore delay is first moment of impulse response
Need higher order moments
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Chapter 7.2 Higher-order Delay Model

Chapter 7.2 Higher-order Delay Model

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Time Moments of Impulse Response h(t) Definition of moments i-th moment

Time Moments of Impulse Response h(t)

Definition of moments

i-th moment

Note that m1

= Elmore delay when h(t) is monotone voltage response of impulse input
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Pade Approximation H(s) can be modeled by Pade approximation of type

Pade Approximation

H(s) can be modeled by Pade approximation of type

(p/q):
where q < p << N

Or modeled by q-th Pade approximation (q << N):

Formulate 2q constraints by matching 2q moments to compute ki’s & pi’s

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General Moment Matching Technique Basic idea: match the moments m-(2q-r), …,

General Moment Matching Technique

Basic idea: match the moments m-(2q-r), …, m-1,

m0, m1, …, mr-1

(i) initial condition matches, i.e.

When r = 2q-1:

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Compute Residues & Poles match first 2q-1 moments EQ1

Compute Residues & Poles

match first 2q-1 moments

EQ1

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Basic Steps for Moment Matching Step 1: Compute 2q moments m-1,

Basic Steps for Moment Matching

Step 1: Compute 2q moments m-1, m0,

m1, …, m(2q-2) of H(s)
Step 2: Solve 2q non-linear equations of EQ1 to get

Step 3: Get approximate waveform

Step 4: Increase q and repeat 1-4, if necessary, for better accuracy

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Components of Moment Matching Model Moment computation Iterative DC analysis on

Components of Moment Matching Model

Moment computation
Iterative DC analysis on transformed equivalent

DC circuit
Recursive computation based on tree traversal
Incremental moment computation
Moment matching methods
Asymptotic Waveform Evaluation (AWE) [Pillage-Rohrer, TCAD’90]
2-pole method [Horowitz, 1984] [Gao-Zhou, ISCAS’93]...
Moment calculation will be provided as an OPTIONAL reading
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Chapter 7 Interconnect Delay 7.1 Elmore Delay 7.2 High-order model and

Chapter 7 Interconnect Delay

7.1 Elmore Delay
7.2 High-order model and moment matching
7.3

Stage delay calculation
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Stage Delay A B C Source Interconnect Load

Stage Delay

A

B

C

Source

Interconnect

Load

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Modeling of Capacitive Load First-order approximation: the driver sees the total

Modeling of Capacitive Load

First-order approximation: the driver sees the total capacitance

of wires and sinks
Problem: Ignore shielding effect of resistance ⇒ pessimistic approximation as driving point admittance
Transform interconnect circuit into a π-model [O’Brian-Savarino, ICCAD’89]
Problem: cannot be easily used with most device models
Compute effective capacitance from π-model [Qian-Pullela-Pileggi, TCAD’94]
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Π-Model [O’Brian-Savarino, ICCAD’89] Moment matching again! Consider the first three moments

Π-Model [O’Brian-Savarino, ICCAD’89]

Moment matching again!
Consider the first three moments of driving point

admittance (moments of response current caused by an applied unit impulse)
Current in the downstream of node k
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Driving-Point Admittance Approximations Driving-point admittance = Sum of voltage moment-weighted subtree

Driving-Point Admittance Approximations

Driving-point admittance = Sum of voltage moment-weighted subtree capacitance
Approximation

of the driving point admittance at the driver

General RC Tree:
lumped RC elements,
distributed RC lines

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Driving-Point Admittance Approximations First order approximation: y(1) = sum of subtree

Driving-Point Admittance Approximations

First order approximation: y(1) = sum of subtree capacitance
Second

order approximation: yk(2) = sum of subtree capacitance weighted by Elmore delay
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Third Order Approximation: Π Model

Third Order Approximation: Π Model

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Current Moment Computation Similar to the voltage moment computation Iterative tree

Current Moment Computation

Similar to the voltage moment computation
Iterative tree traversal:
O(n) run-time,

O(n) storage
Bottom-up tree traversal:
O(n) run-time
Can achieve O(k) storage if we impose order of traversal, k = max degree of a node
O’Brian and Savarino used bottom-up tree traversal
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Bottom-Up Moment Computation Maintain transfer function Hv~w(s) for sink w in

Bottom-Up Moment Computation

Maintain transfer function Hv~w(s) for sink w in subtree

Tv, and moment-weighted capacitance of subtree:

As we merge subtrees, compute new transfer function Hu~v(s) and weighted capacitance recursively:

New transfer function for node w

New moment-weighted capacitance of Tu:

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Current Moment Computation Rule #1

Current Moment Computation Rule #1

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Current Moment Computation Rule #2

Current Moment Computation Rule #2

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Current Moment Computation Rule #3

Current Moment Computation Rule #3

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Current Moment Computation Rule #4 (Merging of Sub-trees) B Branches

Current Moment Computation Rule #4 (Merging of Sub-trees)

B Branches

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Example: Uniform Distributed RC Segment Purely capacitive Wide metal (distributive) Narrow

Example: Uniform Distributed RC Segment

Purely capacitive

Wide metal (distributive)

Narrow metal (distributive)

Narrow metal

(lumped RC)

Wide metal (lumped RC)

Wide metal (π)

Narrow metal (π)

Cload/Cmax

TAB/TAB(0)

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Why Effective Capacitance Model? The π-model is incompatible with existing empirical

Why Effective Capacitance Model?

The π-model is incompatible with existing empirical device

models
Mapping of 4D empirical data is not practical from a storage or run-time point of view
Convert from a π-model to an effective capacitance model for compatibility
Equate the average current in the π-load and the Ceff load
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Equating Average Currents tD = time taken to reach 50% point,

Equating Average Currents

tD = time taken to reach 50% point,
not

50% point of input to 50% point of output
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Waveform Approximation for Vout(t) Quadratic from initial voltage (Vi = VDD

Waveform Approximation for Vout(t)

Quadratic from initial voltage (Vi = VDD for

falling waveform) to 20% point, linear to the 50% point
Voltage waveform and first derivative are continuous at tx
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Average Currents in Capacitors Average current of C1 is not quite

Average Currents in Capacitors

Average current of C1 is not quite as

simple:
Current due to quadratic current in C2
Current due to linear current in C2
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Average current for (0,tx) in C2 Average current for (tx,tD) in

Average current for (0,tx) in C2
Average current for (tx,tD) in C2
Average

current for (0,tD) in C2

Average Currents in C1

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Computation of Effective Capacitance Equating average currents Problem: tD and tx

Computation of Effective Capacitance

Equating average currents
Problem: tD and tx are not

known a priori
Solution: iterative computation
Set the load capacitance equal to total capacitance
Use table-lookup or K-factor equations to obtain tD and tx
Equate average currents and calculate effective capacitance
Set load capacitance equal to effective capacitance and iterate